Icestorm: LDNP (Q) measurements

Code:

  ldnp q0, q1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1159	2031	1	2030	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16218	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldnp q0, q1, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100153	70109	40101	10006	20002	30130	10015	20004	2669141	1779300	1048443	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60205	100082	70114	40108	10004	20002	30134	10014	20004	2669001	1779246	1048433	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60286	20028	10015	40008	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100046	70102	40101	10001	20000	30103	10003	20004	2669152	1779382	1048537	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100092	70103	40101	10002	20000	30103	10003	20004	2669125	1779364	1048526	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669098	1779346	1048515	60110	30212	20008	10004	60476	20088	10048	40037	20000	40100
60204	100420	70166	40137	10013	20016	30227	10047	20024	2669816	1779804	1048760	60172	30241	20028	10015	60224	20008	10004	40001	20000	40100
60204	100045	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	100160	70019	40011	10006	20002	30040	10015	20000	2669411	1779464	1049555	60010	30020	20000	10000	113094	64304	10525	62738	40052	245	69077
78671	130502	85559	48843	10079	26637	38166	10087	20004	2669323	1779436	1049559	60020	30032	20008	10004	60020	20000	10000	40001	20000	0	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669303	1779392	1049511	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669303	1779392	1049511	60010	30020	20000	10000	60110	20028	10015	40008	20000	0	40010
60024	100059	70013	40011	10002	20000	30010	10000	20000	2669303	1779392	1049511	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60025	100082	70024	40018	10004	20002	30044	10014	20000	2669573	1779572	1049621	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669384	1779446	1049544	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
63798	113242	71998	41550	9537	20911	31776	9552	20000	2669573	1779572	1049621	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669384	1779446	1049544	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669303	1779392	1049511	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldnp q0, q1, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	100153	70109	40101	10006	20002	30130	10014	20004	2669084	1779262	1048420	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100047	70103	40101	10002	20000	30103	10003	20024	2669536	1779628	1048654	60172	30241	20028	10015	60224	20008	10004	40001	20000	0	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	71354	31113	10063	44892	25871	69	47326
60204	100107	70103	40101	10002	20000	30103	10003	20004	2669190	1779372	1048510	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20024	2671378	1780858	1049402	60171	30242	20028	10014	60224	20008	10004	40001	20000	0	40100
60204	100052	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100253	70019	40011	10006	20002	30040	10015	20004	2669229	1779338	1049477	60020	30032	20008	10004	60020	20000	10000	40001	20000	40010
60024	100139	70014	40011	10003	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20024	2669896	1779808	1049748	60082	30061	20028	10015	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60102	20028	10015	40008	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100051	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100050	70013	40011	10002	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 4: throughput

Count: 8

Code:

  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]
  ldnp q0, q1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80216	160131	101	160030	100	160008	300	560006	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160056	300	1280812	0	160156	200	160068	0	200	160068	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80050	160101	101	160000	100	160200	300	1210996	0	160300	200	160236	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80202	160045	11	160034	10	160008	30	1280248	160018	20	160012	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160025	80107	160045	11	160034	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80066	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10

LDNP (Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations