Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDNP (S)

Test 1: uops

Code:

  ldnp s0, s1, [x6]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
2005115220311203020001616420002000200012000
2004105120011200020001616420002000200012000
2004105120011200020001616420002000200012000
2004105120011200020001616420002000200012000
2004105120011200020001616420002000200012000
2004105120011200020001616420002000200012000
2004105120011200020001616420002000200012000
2004105120011200020001616420002000200012000
2004105120011200020001616420002000200012000
2004105120011200020001616420002000200012000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldnp s0, s1, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602051001557010940101100062000230130100152000426691651779316104845360110302122000810004602242000810004400012000040100
602041001727011940110100052000430134100142000426697461779778104877960110302122000810004602242000810004400012000040100
602041000547010340101100022000030103100032000426706641780390104915360110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602051002077011640110100042000230135100132000426694491779580104865860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032002426695421779636104865960172302452002810015602242000810004400012000040100
602041000507010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600251001527001940011100062000230040100152000426690821779236104941460020300322000810004600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000601102002810015400082000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600251000757002340018100032000230044100142000026697621779698104969860010300202000010000600202000010000400012000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldnp s0, s1, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602051001537010940101100062000230130100152000426691271779326104848160110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041001377010440101100032000030103100032000426690171779292104848260110302122000810004602242000810004400012000040100
602041000457010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602902002810015400082000040100
602041000477010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600261035897002940017100082000430070100262000426692321779342104947460020300302000810004600442000810004400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000601062002810015400082000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000601042002810015400082000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010

Test 4: throughput

Count: 8

Code:

  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1602058015616013110101600301000160008300560188016010820016001202001600681160000100
16020480059160101101016000010001600083001280012016010820016001202001600121160000100
16020480045160101101016000010001600083001280012016010820016001202001600121160000100
16020480045160101101016000010001600083001280012016010820016001202001600121160000100
16020480254160101101016000010001600083001281904016010820016001202001601241160000100
17476213771117209478083164283730931600083001281094016010820016001202001600121160000100
1602048004716010110101600001000160008300512188016010820016001202001600121160000100
16020480048160101101016000010001600083001280012016010820016001202001600121160000100
16020480045160101101016000010001600083001280012016010820016001202001600121160000100
16020480045160101101016000010001600083001280012016010820016001202001600681160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
16002580184160041111600301016000030640218016001020160000020160000116000010
160024800541600111116000010160000301279998016001020160000020160000116000010
160024800451600111116000010160000301279998016001020160000020160000116000010
160024800451600111116000010160000301279998016001020160000020160000116000010
160024800451600111116000010160000301279998016001020160000020160000116000010
160024800451600111116000010160000301279998016001020160000020160000116000010
160024800451600111116000010160000301279998016001020160000020160000116000010
160025804081600411116003010160000301280790016001020160000020160000116000010
160024800651600111116000010160008301280302016001820160012020160000116000010
160024800451600111116000010160000301279998016001020160000020160000116000010