Icestorm: LDNP (S) measurements

Code:

  ldnp s0, s1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1152	2031	1	2030	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldnp s0, s1, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100155	70109	40101	10006	20002	30130	10015	20004	2669165	1779316	1048453	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100172	70119	40110	10005	20004	30134	10014	20004	2669746	1779778	1048779	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100054	70103	40101	10002	20000	30103	10003	20004	2670664	1780390	1049153	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60205	100207	70116	40110	10004	20002	30135	10013	20004	2669449	1779580	1048658	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20024	2669542	1779636	1048659	60172	30245	20028	10015	60224	20008	10004	40001	20000	40100
60204	100050	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100152	70019	40011	10006	20002	30040	10015	20004	2669082	1779236	1049414	60020	30032	20008	10004	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60110	20028	10015	40008	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60025	100075	70023	40018	10003	20002	30044	10014	20000	2669762	1779698	1049698	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldnp s0, s1, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100153	70109	40101	10006	20002	30130	10015	20004	2669127	1779326	1048481	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100137	70104	40101	10003	20000	30103	10003	20004	2669017	1779292	1048482	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100045	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60290	20028	10015	40008	20000	40100
60204	100047	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60026	103589	70029	40017	10008	20004	30070	10026	20004	2669232	1779342	1049474	60020	30030	20008	10004	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60106	20028	10015	40008	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60104	20028	10015	40008	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 4: throughput

Count: 8

Code:

  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]
  ldnp s0, s1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80156	160131	101	0	160030	100	0	160008	300	560188	0	160108	200	160012	0	200	160068	1	160000	100
160204	80059	160101	101	0	160000	100	0	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	0	160000	100	0	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	0	160000	100	0	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80254	160101	101	0	160000	100	0	160008	300	1281904	0	160108	200	160012	0	200	160124	1	160000	100
174762	137711	172094	7808	3	164283	7309	3	160008	300	1281094	0	160108	200	160012	0	200	160012	1	160000	100
160204	80047	160101	101	0	160000	100	0	160008	300	512188	0	160108	200	160012	0	200	160012	1	160000	100
160204	80048	160101	101	0	160000	100	0	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	0	160000	100	0	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	0	160000	100	0	160008	300	1280012	0	160108	200	160012	0	200	160068	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80184	160041	11	160030	10	160000	30	640218	0	160010	20	160000	0	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1279998	0	160010	20	160000	0	20	160000	1	160000	10
160024	80045	160011	11	160000	10	160000	30	1279998	0	160010	20	160000	0	20	160000	1	160000	10
160024	80045	160011	11	160000	10	160000	30	1279998	0	160010	20	160000	0	20	160000	1	160000	10
160024	80045	160011	11	160000	10	160000	30	1279998	0	160010	20	160000	0	20	160000	1	160000	10
160024	80045	160011	11	160000	10	160000	30	1279998	0	160010	20	160000	0	20	160000	1	160000	10
160024	80045	160011	11	160000	10	160000	30	1279998	0	160010	20	160000	0	20	160000	1	160000	10
160025	80408	160041	11	160030	10	160000	30	1280790	0	160010	20	160000	0	20	160000	1	160000	10
160024	80065	160011	11	160000	10	160008	30	1280302	0	160018	20	160012	0	20	160000	1	160000	10
160024	80045	160011	11	160000	10	160000	30	1279998	0	160010	20	160000	0	20	160000	1	160000	10

LDNP (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations