Icestorm: LDNP (signed offset, D) measurements

Code:

  ldnp d0, d1, [x6, #0x10]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1290	2031	1	2030	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1043	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1043	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1043	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1043	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1043	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1043	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1043	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1043	2001	1	2000	2000	16164	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldnp d0, d1, [x6, #0x10]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	100259	70109	40101	10006	20002	30130	10015	20004	2669127	1779326	1048480	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668938	1779200	1048404	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60205	100155	70113	40108	10003	20002	30134	10014	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2669098	1779346	1048515	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100155	70019	40011	10006	20002	30040	10015	20024	2669599	1779540	1049542	60082	30061	20028	10015	60044	20008	10004	40001	20000	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60025	100075	70023	40018	10003	20002	30044	10014	20000	2669411	1779464	1049555	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	49104	3399923	2241879	1061315	126527	83336	54420	10354	60044	20008	10004	40001	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldnp d0, d1, [x6, #0x10]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0050

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60204	100103	70103	40101	10002	20000	30103	10003	20004	2671017	1780586	1049251	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60205	100723	70113	40108	10003	20002	30134	10014	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669314	1779490	1048603	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100050	70103	40101	10002	20000	30103	10003	20004	2669206	1779418	1048559	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100155	70019	40011	10006	20002	30040	10015	20000	2669197	1779282	1049421	60010	30020	20000	10000	60110	20028	10015	40008	20000	40010
60024	100053	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100050	70013	40011	10002	20000	30010	10000	20000	2669546	1779554	1049610	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 4: throughput

Count: 8

Code:

  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]
  ldnp d0, d1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80162	160137	101	160036	100	160008	300	560242	160108	200	160012	200	160012	1	160000	100
160204	80056	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80170	160047	11	160036	10	160000	30	640164	0	160010	20	160000	0	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	0	160010	20	160000	0	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	0	160010	20	160000	0	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	0	160010	20	160000	0	20	160000	1	160000	10
160025	80105	160045	11	160034	10	160000	30	1282360	0	160010	20	160000	0	20	160000	1	160000	10
160024	80056	160011	11	160000	10	160000	30	1280326	0	160010	20	160000	0	20	160000	1	160000	10
160024	80059	160011	11	160000	10	166743	115234	1196186	1007	175131	11869	168054	76	20	160012	1	160000	10
160024	80059	160011	11	160000	10	160000	30	1280218	0	160010	20	160000	0	20	160000	1	160000	10
160025	80107	160045	11	160034	10	160000	30	1280992	0	160010	20	160000	0	20	160000	1	160000	10
160024	80060	160011	11	160000	10	160000	30	1280434	0	160010	20	160000	0	20	160000	1	160000	10

LDNP (signed offset, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations