Icestorm: LDNP (signed offset, Q) measurements

Code:

  ldnp q0, q1, [x6, #0x10]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1157	2031	1	2030	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldnp q0, q1, [x6, #0x10]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100159	70109	40101	10006	20002	30130	10015	20004	2669193	1779374	1048510	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100106	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60205	100140	70113	40108	10003	20002	30134	10014	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100063	70103	40101	10002	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100151	70019	40011	10006	20002	30040	10015	20004	2669593	1779616	1049669	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60025	100082	70024	40018	10004	20002	30044	10014	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669141	1779284	1049445	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20020	2671580	1780902	1050406	60072	30053	20020	10011	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldnp q0, q1, [x6, #0x10]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100295	70109	40101	10006	20002	30130	10015	20004	2669273	1779388	1048497	60110	30212	20008	10004	60290	20028	10015	40008	20000	40100
60204	100054	70102	40101	10001	20000	30103	10003	20004	2669368	1779526	1048625	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100054	70102	40101	10001	20000	30103	10003	20004	2669368	1779526	1048625	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100054	70102	40101	10001	20000	30103	10003	20004	2669368	1779526	1048625	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100054	70102	40101	10001	20000	30103	10003	20004	2669368	1779526	1048625	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100054	70102	40101	10001	20000	30103	10003	20004	2669368	1779526	1048625	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100098	70102	40101	10001	20000	30103	10003	20004	2669557	1779652	1048702	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100054	70102	40101	10001	20000	30103	10003	20004	2669368	1779526	1048625	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100055	70102	40101	10001	20000	30103	10003	20004	2670610	1780354	1049131	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100054	70102	40101	10001	20000	30103	10003	20004	2669368	1779526	1048625	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0043

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	100162	70019	40011	10006	20002	30040	10015	20004	2669946	1779812	1049766	60020	30032	20008	10004	60044	20008	10004	40001	20000	0	40010
60024	100074	70014	40011	10003	20000	30010	10000	20045	2746730	1831027	1110927	60143	30093	20049	10025	60020	20000	10000	40001	20000	0	40010
60024	100102	70013	40011	10002	20000	30013	10003	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100043	70012	40011	10001	20000	30010	10000	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100146	70028	40020	10004	20004	30041	10011	20000	2669222	1779338	1049478	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100041	70012	40011	10001	20000	30010	10000	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60025	100240	70040	40027	10007	20006	30075	10025	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100041	70012	40011	10001	20000	30010	10000	20000	2669168	1779302	1049456	60010	30020	20000	10000	60082	20020	10011	40010	20000	0	40010
60024	100041	70012	40011	10001	20000	30010	10000	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010

Test 4: throughput

Count: 8

Code:

  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]
  ldnp q0, q1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	80217	160133	101	0	160032	100	0	160008	300	633596	0	160108	200	160012	0	200	160012	0	1	160000	0	100
160204	80057	160101	101	0	160000	100	0	160008	300	1280266	0	160108	200	160012	0	200	160012	0	1	160000	0	100
160204	80057	160101	101	0	160000	100	0	160008	300	1280266	0	160108	200	160012	0	200	160012	0	1	160000	0	100
160204	80057	160101	101	0	160000	100	0	160008	300	1280266	0	160108	200	160012	0	200	160012	0	1	160000	0	100
160204	80057	160101	101	0	160000	100	0	160008	300	1280266	0	160108	200	160012	0	200	160012	0	1	160000	0	100
160204	80057	160101	101	0	160000	100	0	160056	300	1280868	0	160156	200	160068	0	200	160012	0	1	160000	0	100
160204	80057	160101	101	0	160000	100	0	160008	300	1287016	0	160108	200	160012	0	200	160012	0	1	160000	0	100
160204	80086	160101	101	0	160000	100	0	160008	300	1280374	0	160108	200	160012	0	200	160012	0	1	160000	0	100
160204	80057	160101	101	0	160000	100	0	160008	300	1280266	0	160108	200	160012	0	200	160012	0	1	160000	0	100
160204	80057	160101	101	0	160000	100	0	160008	300	1280266	0	160108	200	160012	0	200	160012	0	1	160000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80179	160047	11	160036	10	160008	30	640008	160018	20	160012	20	160068	1	160000	10
160024	80118	160011	11	160000	10	160000	30	1279984	160010	20	160000	20	160000	1	160000	10
160024	80044	160011	11	160000	10	160000	30	1279984	160010	20	160000	20	160000	1	160000	10
160024	80044	160011	11	160000	10	160000	30	1279984	160010	20	160000	20	160000	1	160000	10
160024	80044	160011	11	160000	10	160057	30	1280649	160067	20	160068	20	160000	1	160000	10
160024	80052	160011	11	160000	10	160000	30	1279984	160010	20	160000	20	160000	1	160000	10
160024	80044	160011	11	160000	10	160000	30	1279984	160010	20	160000	20	160000	1	160000	10
160024	80044	160011	11	160000	10	160000	30	1280146	160010	20	160000	20	160068	1	160000	10
160024	80049	160011	11	160000	10	160000	30	1279984	160010	20	160000	20	160000	1	160000	10
160024	80062	160011	11	160000	10	160000	30	1280254	160010	20	160000	20	160000	1	160000	10

LDNP (signed offset, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations