Icestorm: LDNP (signed offset, S) measurements

Code:

  ldnp s0, s1, [x6, #0x10]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1164	2031	1	2030	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldnp s0, s1, [x6, #0x10]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60206	100187	70120	40108	10008	20004	30161	10026	20004	2669276	1779390	1048498	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70102	40101	10001	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100040	70102	40101	10001	20000	30103	10003	20024	2669347	1779502	1048576	60172	30241	20028	10015	60224	20008	10004	40001	20000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	100276	70019	40011	10006	20002	30040	10015	20004	2669271	1779362	1049491	60020	30032	20008	10004	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60102	20028	10015	40008	20000	0	40010
60024	100051	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100070	70012	40011	10001	20000	30010	10000	20000	2669195	1779320	1049467	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20024	2669491	1779538	1049586	60082	30061	20028	10015	60020	20000	10000	40001	20000	0	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldnp s0, s1, [x6, #0x10]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	100155	70109	40101	10006	20002	30130	10015	20004	2669190	1779372	1048510	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60205	100091	70115	40108	10005	20002	30134	10014	20306	2260505	1478759	844068	59371	33967	21000	8038	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669638	1779706	1048735	60110	30212	20008	10004	60472	20088	10047	40035	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	101163	70166	40137	10013	20016	30231	10047	20004	2669287	1779472	1048592	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60205	100077	70113	40108	10003	20002	30134	10014	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100438	70168	40139	10013	20016	30231	10047	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	100149	70019	40011	10006	20002	30040	10015	20004	2669622	1779596	1049634	60020	30032	20008	10004	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20024	2671198	1780680	1050282	60082	30065	20028	10015	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2671274	1780706	1050314	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2670734	1780346	1050094	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010

Test 4: throughput

Count: 8

Code:

  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]
  ldnp s0, s1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	80169	160137	101	0	160036	100	0	160008	300	512260	160108	200	160012	200	160068	0	1	160000	0	100
160204	80112	160101	101	0	160000	100	0	160008	300	1280012	160108	200	160012	200	160012	0	1	160000	0	100
160204	80045	160101	101	0	160000	100	0	160008	300	1280012	160108	200	160012	200	160012	0	1	160000	0	100
160204	80048	160101	101	0	160000	100	0	160008	300	1280012	160108	200	160012	200	160012	0	1	160000	0	100
160204	80045	160101	101	0	160000	100	0	160008	300	1280174	160108	200	160012	20223	158736	167	10027	150016	86	12450
160204	80107	160101	101	0	160000	100	0	160008	300	1280028	160108	200	160012	200	160012	0	1	160000	0	100
160204	80146	160101	101	0	160000	100	0	160008	300	960114	160108	200	160012	200	160012	0	1	160000	0	100
160204	80073	160101	101	0	160000	100	0	160008	300	960068	160108	200	160012	200	160012	0	1	160000	0	100
160204	80045	160101	101	0	160000	100	0	160008	300	1280012	160108	200	160012	200	160012	0	1	160000	0	100
160204	80045	160101	101	0	160000	100	0	160008	300	1280012	160108	200	160012	200	160012	0	1	160000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80180	160045	11	160034	10	160000	30	640164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160025	80349	160041	11	160030	10	160000	30	1280272	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80226	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10

LDNP (signed offset, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations