Icestorm: LDP (D) measurements

Code:

  ldp d0, d1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1159	2031	1	2030	2000	16182	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100162	70109	40101	10006	20002	30130	10015	20004	2669141	1779300	1048443	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100043	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100044	70102	40101	10001	20000	30103	10003	20004	2669098	1779346	1048515	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100046	70102	40101	10001	20000	30103	10003	20004	2669125	1779364	1048526	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100045	70102	40101	10001	20000	30103	10003	20024	2669755	1779776	1048742	60172	30245	20028	10015	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669152	1779382	1048537	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100052	70102	40101	10001	20000	30103	10003	20004	2669343	1779470	1048567	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0043

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60024	100052	70013	40011	10002	20000	30013	10003	75691	4198170	2716832	1375021	207952	146467	83778	13749	60208	20061	10032	40027	20000	0	40010
60025	100410	70073	40045	10014	20014	30143	10047	20165	2679246	1785910	1054201	60523	30289	20169	10091	60142	20041	10021	40018	20000	0	40010
60024	100045	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100134	70014	40011	10003	20000	30013	10003	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100043	70012	40011	10001	20000	30010	10000	20000	2669141	1779284	1049445	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100045	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100043	70012	40011	10001	20000	30010	10000	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100040	70012	40011	10001	20000	30010	10000	20026	2669349	1779448	1049527	60082	30060	20030	10014	60020	20000	10000	40001	20000	0	40010
60024	100043	70012	40011	10001	20000	30010	10000	20000	2669168	1779302	1049456	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100145	70109	40101	10006	20002	30130	10015	20004	2669208	1779380	1048514	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100056	70103	40101	10002	20000	30103	10003	20004	2669181	1779362	1048503	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669136	1779336	1048488	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60205	100077	70113	40105	10004	20004	30133	10014	20004	2669640	1779668	1048690	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669287	1779472	1048592	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60282	20028	10015	40008	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100353	70019	40011	10006	20002	30040	10015	20004	2669188	1779346	1049504	60020	30032	20008	10004	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20024	2669422	1779492	1049560	60082	30063	20028	10015	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20024	2669524	1779564	1049610	60082	30065	20028	10015	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60025	100073	70023	40018	10003	20002	30044	10014	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 4: throughput

Count: 8

Code:

  ldp d0, d1, [x6]
  ldp d0, d1, [x6]
  ldp d0, d1, [x6]
  ldp d0, d1, [x6]
  ldp d0, d1, [x6]
  ldp d0, d1, [x6]
  ldp d0, d1, [x6]
  ldp d0, d1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80172	160135	101	160034	100	160008	300	496188	160108	200	160012	200	160012	1	160000	100
160204	80056	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280066	160108	200	160012	200	160012	1	160000	100
160204	80048	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80155	160041	11	160030	10	160008	30	640242	160018	20	160012	20	160000	1	160000	10
160024	80053	160011	11	160000	10	160010	30	836194	160020	20	160014	20	160012	1	160000	10
160024	80049	160011	11	160000	10	160000	30	1279982	160010	20	160000	20	160000	1	160000	10
160024	80043	160011	11	160000	10	160000	30	1279982	160010	20	160000	20	160000	1	160000	10
160024	80048	160011	11	160000	10	160000	30	1279982	160010	20	160000	20	160000	1	160000	10
160024	80043	160011	11	160000	10	160000	30	1279982	160010	20	160000	20	160000	1	160000	10
160024	80043	160011	11	160000	10	160000	30	1279982	160010	20	160000	20	160000	1	160000	10
160024	80049	160011	11	160000	10	160058	30	867218	160068	20	160070	20	160000	1	160000	10
160024	80043	160011	11	160000	10	160000	30	1279982	160010	20	160000	20	160000	1	160000	10
160024	80043	160011	11	160000	10	160000	30	1279982	160010	20	160000	20	160000	1	160000	10

LDP (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations