Icestorm: LDP (Q) measurements

Code:

  ldp q0, q1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1160	2031	1	2030	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp q0, q1, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100153	70109	40101	10006	20002	30130	10015	20004	2669141	1779300	1048443	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60290	20028	10015	40008	20000	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60282	20028	10015	40008	20000	40100
60205	100091	70113	40108	10003	20002	30134	10014	20004	2669046	1779272	1048448	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2671069	1780660	1049318	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100059	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100158	70019	40011	10006	20002	30040	10015	20000	2669303	1779392	1049511	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100053	70013	40011	10002	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60102	20028	10015	40008	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669168	1779302	1049456	60010	30020	20000	10000	60044	20008	10004	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp q0, q1, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	100150	70109	40101	10006	20002	30130	10015	20004	2669168	1779318	1048454	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100152	70103	40101	10002	20000	30103	10003	20004	2669422	1779562	1048647	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100052	70103	40101	10002	20000	30103	10003	20004	2669287	1779472	1048592	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60282	20028	10015	40008	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	100158	70019	40011	10006	20002	30040	10015	20004	2669283	1779374	1049499	60020	30032	20008	10004	60020	20000	10000	40001	20000	0	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669168	1779302	1049456	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60025	100079	70023	40018	10003	20002	30041	10011	20000	2669411	1779464	1049555	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100043	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	63240	25602	10130	41319	22661	39	41899
60024	100051	70013	40011	10002	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60106	20028	10015	40008	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
64821	115757	74077	42487	10058	21532	32312	10056	20000	2669384	1779446	1049544	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010

Test 4: throughput

Count: 8

Code:

  ldp q0, q1, [x6]
  ldp q0, q1, [x6]
  ldp q0, q1, [x6]
  ldp q0, q1, [x6]
  ldp q0, q1, [x6]
  ldp q0, q1, [x6]
  ldp q0, q1, [x6]
  ldp q0, q1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80567	160137	101	160036	100	160008	300	496188	0	160108	200	160012	0	200	160012	1	160000	100
160204	80053	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280194	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	0	160108	200	160012	0	200	160012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80161	160041	11	160030	10	160056	30	640346	160066	20	160068	20	160012	1	160000	10
160025	80186	160041	11	160030	10	160008	30	1280414	160018	20	160012	20	160000	1	160000	10
160024	80045	160011	11	160000	10	160000	30	1280144	160010	20	160000	20	160000	1	160000	10
160024	80048	160011	11	160000	10	160000	30	1280006	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280160	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1279998	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1279998	160010	20	160000	20	160000	1	160000	10
160024	80045	160011	11	160000	10	160000	30	1280088	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160056	30	699236	160066	20	160068	20	160000	1	160000	10
160024	80045	160011	11	160000	10	160000	30	1279998	160010	20	160000	20	160000	1	160000	10

LDP (Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations