Icestorm: LDP (S) measurements

Code:

  ldp s0, s1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1149	2031	1	2030	2000	16254	2000	2000	2000	1	2000
2004	1045	2001	1	2000	2000	15998	2000	2000	2000	1	2000
2004	1045	2001	1	2000	2000	15998	2000	2000	2000	1	2000
2004	1048	2001	1	2000	2000	15998	2000	2000	2000	1	2000
2004	1050	2001	1	2000	2000	16066	2000	2000	2000	1	2000
2004	1050	2001	1	2000	2000	15998	2000	2000	2000	1	2000
2004	1050	2001	1	2000	2000	15998	2000	2000	2000	1	2000
2004	1045	2001	1	2000	2000	15998	2000	2000	2000	1	2000
2004	1045	2001	1	2000	2000	16066	2000	2000	2000	1	2000
2004	1046	2001	1	2000	2000	15998	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	100155	70109	40101	10006	20002	30130	10015	20004	2669038	1779194	1048356	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60282	20028	10015	40008	20000	0	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100122	70103	40101	10002	20000	30103	10003	20004	2669638	1779706	1048735	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60205	100080	70114	40108	10004	20002	30134	10014	20004	2669226	1779422	1048567	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669098	1779346	1048515	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100045	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100162	70019	40011	10006	20002	30040	10015	20004	2670042	1779882	1049804	60020	30030	20008	10004	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30013	10003	20024	2669626	1779628	1049639	60082	30065	20028	10015	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30013	10003	20004	2669269	1779400	1049537	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30013	10003	20004	2669269	1779400	1049537	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30013	10003	20004	2669269	1779400	1049537	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30013	10003	20004	2669269	1779400	1049537	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100051	70013	40011	10002	20000	30013	10003	20004	2669404	1779490	1049592	60020	30032	20008	10004	60104	20028	10015	40008	20000	40010
60025	100106	70024	40018	10004	20002	30044	10014	20004	2669966	1779858	1049850	60020	30032	20008	10004	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	100151	70109	40101	10006	20002	30130	10015	20004	2668952	1779174	1048366	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60290	20032	10015	40005	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100
60204	100042	70102	40101	10001	20000	30103	10003	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	100155	70019	40011	10006	20002	30040	10015	20004	2669229	1779338	1049477	60020	30032	20008	10004	60044	20008	10004	40001	20000	0	40010
60024	100047	70013	40011	10002	20000	30013	10003	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60025	100080	70024	40018	10004	20002	30044	10014	20000	2669762	1779698	1049698	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100047	70013	40011	10002	20000	30010	10000	20024	2670189	1780002	1050050	60082	30064	20028	10015	60110	20028	10015	40008	20000	0	40010

Test 4: throughput

Count: 8

Code:

  ldp s0, s1, [x6]
  ldp s0, s1, [x6]
  ldp s0, s1, [x6]
  ldp s0, s1, [x6]
  ldp s0, s1, [x6]
  ldp s0, s1, [x6]
  ldp s0, s1, [x6]
  ldp s0, s1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80181	160135	101	160034	100	160008	300	813252	160108	200	160012	200	160012	1	160000	100
160206	80515	160163	103	160060	102	160804	23313	1246318	162001	1771	160932	200	160124	1	160000	100
160204	80061	160105	101	160004	100	160008	300	1280136	160108	200	160012	202	160070	2	160000	100
160204	80046	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100
160204	80099	160105	101	160004	100	160008	300	512022	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	672022	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160068	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80050	160101	101	160000	100	160008	300	1280150	160108	200	160012	200	160012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160026	80255	160075	11	160064	10	160008	30	1280194	160018	20	160012	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160025	80376	160041	11	160030	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160025	80117	160041	11	160030	10	160000	30	1280380	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	160010	20	160000	20	160000	1	160000	10

LDP (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations