Icestorm: LDP (post-index, D) measurements

Code:

  ldp d0, d1, [x6], #0x10

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1813	3057	1027	2030	1026	2000	3516	25047	3000	2000	2000	1001	2000
2004	1573	3001	1001	2000	1000	2000	3516	24678	3000	2000	2000	1001	2000
2004	1516	3001	1001	2000	1000	2000	3516	24687	3000	2000	2000	1001	2000
2004	1582	3001	1001	2000	1000	2000	3516	26973	3000	2000	2000	1001	2000
2004	1527	3001	1001	2000	1000	2000	3516	24777	3000	2000	2000	1001	2000
2004	1515	3001	1001	2000	1000	2000	3516	24687	3000	2000	2056	1027	2000
2004	1554	3001	1001	2000	1000	2000	3516	24714	3000	2000	2000	1001	2000
2004	1542	3001	1001	2000	1000	2000	3516	24642	3000	2000	2000	1001	2000
2004	1515	3001	1001	2000	1000	2000	3516	24552	3000	2000	2000	1001	2000
2004	1524	3001	1001	2000	1000	2000	3516	24615	3000	2000	2000	1001	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6], #0x10
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0084

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60214	102425	80232	50112	10100	20020	40385	10089	20006	2661044	1568794	789475	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100140	80104	50101	10003	20000	40104	10003	20024	2664505	1570982	790539	70173	30239	20028	10013	60218	20008	10003	50001	20000	40100
60204	100074	80104	50101	10003	20000	40104	10003	20006	2660577	1568480	789326	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100083	80104	50101	10003	20000	40104	10003	20006	2660423	1568382	789282	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100086	80104	50101	10003	20000	40104	10003	20006	2660369	1568346	789262	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100084	80104	50101	10003	20000	40104	10003	20006	2660342	1568326	789255	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100098	80104	50101	10003	20000	40104	10003	20006	2662367	1569678	789888	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100083	80104	50101	10003	20000	40104	10003	20006	2660288	1568292	789237	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100078	80104	50101	10003	20000	40104	10003	20006	2660207	1568238	789210	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100086	80104	50101	10003	20000	40104	10003	20006	2660288	1568292	789238	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0066

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60034	102274	80138	50021	10097	20020	40294	10083	20024	2663665	1571920	791021	70082	30059	20026	10013	60038	20008	10003	50001	20000	0	40010
60024	100066	80014	50011	10003	20000	40014	10003	20000	2660059	1569684	789897	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789897	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789897	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789897	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789897	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60025	100142	80029	50019	10008	20002	40046	10013	20000	2660059	1569684	789897	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789897	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789897	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789897	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6], #0x10
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0089

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60214	102400	80228	50112	10096	20020	40385	10089	20006	2660590	1568428	789315	70113	30209	20008	10003	60278	20028	10013	50009	20000	0	40100
60204	100085	80104	50101	10003	20000	40104	10003	20006	2660477	1568410	789300	70113	30209	20008	10003	60218	20008	10003	50001	20000	0	40100
60204	100084	80104	50101	10003	20000	40104	10003	20006	2660774	1568584	789398	70113	30209	20008	10003	60218	20008	10003	50001	20000	0	40100
60204	100083	80104	50101	10003	20000	40104	10003	20006	2660720	1568548	789380	70113	30209	20008	10003	60218	20008	10003	50001	20000	0	40100
60204	100083	80104	50101	10003	20000	40104	10003	20006	2660369	1568338	789264	70113	30209	20008	10003	60218	20008	10003	50001	20000	0	40100
60204	100094	80105	50101	10004	20000	40104	10003	20006	2660720	1568548	789381	70113	30209	20008	10003	60218	20008	10003	50001	20000	0	40100
60204	100083	80104	50101	10003	20000	40104	10003	20023	2662512	1560104	794197	70171	30238	20026	10013	60218	20008	10003	50001	20000	0	40100
60204	100084	80104	50101	10003	20000	40104	10003	20006	2660612	1568500	789343	70113	30209	20008	10003	60218	20008	10003	50001	20000	0	40100
60204	100202	80122	50112	10006	20004	40139	10012	20006	2660396	1568356	789273	70113	30209	20008	10003	60218	20008	10003	50001	20000	0	40100
60204	100080	80104	50101	10003	20000	40104	10003	20006	2660450	1568392	789290	70113	30209	20008	10003	60218	20008	10003	50001	20000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0073

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60034	102421	80140	50021	10099	20020	40294	10084	20006	2660663	1570058	790079	70022	30029	20006	10003	60020	20000	10000	50001	20000	0	40010
60024	100080	80014	50011	10003	20000	40010	10000	20000	2660194	1569780	789938	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100071	80013	50011	10002	20000	40010	10000	20000	2660194	1569780	789938	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60025	100144	80028	50019	10007	20002	40046	10013	20000	2660248	1569816	789954	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100074	80013	50011	10002	20000	40010	10000	20000	2660275	1569830	789964	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100092	80013	50011	10002	20000	40010	10000	20000	2660599	1570050	790065	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100085	80013	50011	10002	20000	40010	10000	20000	2660518	1569996	790040	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60025	100158	80028	50019	10007	20002	40046	10013	20000	2660869	1570228	790156	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100119	80013	50011	10002	20000	40010	10000	20000	2660518	1569996	790037	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100071	80013	50011	10002	20000	40010	10000	20024	2661841	1570810	790478	70083	30059	20028	10013	60020	20000	10000	50001	20000	0	40010

Test 4: throughput

Count: 8

Code:

  ldp d0, d1, [x6], #0x10
  ldp d0, d1, [x7], #0x10
  ldp d0, d1, [x8], #0x10
  ldp d0, d1, [x9], #0x10
  ldp d0, d1, [x10], #0x10
  ldp d0, d1, [x11], #0x10
  ldp d0, d1, [x12], #0x10
  ldp d0, d1, [x13], #0x10

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0794

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160214	88639	240667	80367	160300	80368	160009	240318	1393767	240115	200	160012	200	160012	80005	160000	100
160204	86363	240105	80105	160000	80106	160009	240318	1393511	240115	200	160012	200	160012	80005	160000	100
160204	86352	240105	80105	160000	80106	160009	240318	1393511	240115	200	160012	200	160012	80005	160000	100
160204	86352	240105	80105	160000	80106	160009	240318	1393511	240115	200	160012	200	160012	80005	160000	100
160204	86352	240105	80105	160000	80106	160009	240318	1393511	240115	200	160012	200	160012	80005	160000	100
160204	86352	240105	80105	160000	80106	160009	240318	1393511	240115	200	160012	200	160012	80005	160000	100
160204	86352	240105	80105	160000	80106	160009	240318	1393511	240115	200	160012	200	160012	80005	160000	100
160204	86356	240105	80105	160000	80106	160008	240318	1393606	240114	200	160012	200	160012	80005	160000	100
160204	86351	240105	80105	160000	80106	160008	240318	1393498	240114	200	160012	200	160012	80005	160000	100
160205	86417	240161	80131	160030	80132	160008	240318	1393736	240114	200	160012	200	160012	80005	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0794

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160034	88299	240585	80285	160300	80286	160011	240051	1392853	0	240028	20	160014	0	20	160000	80001	160000	10
160024	86349	240011	80011	160000	80010	160000	240030	1393421	0	240010	20	160000	0	20	160000	80001	160000	10
160024	86348	240011	80011	160000	80010	160000	240030	1393421	0	240010	20	160000	0	20	160000	80001	160000	10
160024	86348	240011	80011	160000	80010	160000	240030	1393421	0	240010	20	160000	0	20	160068	80031	160000	10
160024	86348	240011	80011	160000	80010	160000	240030	1393421	0	240010	20	160000	0	20	160000	80001	160000	10
160024	86348	240011	80011	160000	80010	160000	240030	1393421	0	240010	20	160000	0	20	160000	80001	160000	10
160024	86348	240011	80011	160000	80010	160000	240030	1393594	0	240010	20	160000	0	20	160068	80031	160000	10
160024	86346	240011	80011	160000	80010	160000	240030	1393511	0	240010	20	160000	0	20	160000	80001	160000	10
160024	86348	240011	80011	160000	80010	160000	240030	1393561	0	240010	20	160000	0	20	160000	80001	160000	10
160024	86353	240011	80011	160000	80010	160000	240030	1393421	0	240010	20	160000	0	20	160000	80001	160000	10

LDP (post-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations