Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDP (post-index, S)

Test 1: uops

Code:

  ldp s0, s1, [x6], #0x10
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
200519373113105320601052204836172687030742056200010012000
200416113001100120001000200035222532130002000205610272000
200415553001100120001000200035202496830002000205610272000
200415983001100120001000200035202494130002000200010012000
200415963001100120001000200035262483730002000200010012000
200415463001100120001000200035202492330002000200010012000
200415873001100120001000200035202537330002000200010012000
200416143057102720301026200035202522930002000200010012000
200415523001100120001000200035202511230002000200010012000
200415443001100120001000200035202559830002000200010012000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6], #0x10
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0072

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60214102284802315011210099200204038510089200062659942156800478911070113302092000810003602782002810013500092000040100
60204100097801045010110003200004010410002200062660832156858078938670113302092000810003602182000810003500012000040100
60204100146801045010110003200004010410003200062660693156856078937170113302092000810003602182000810003500012000040100
60204100066801045010110003200004010410003200062660342156832878925670113302092000810003602182000810003500012000040100
60204100066801045010110003200004010410003200062659991156809478914470113302092000810003602182000810003500012000040100
60204100066801045010110003200004010410003200062659991156809478914470113302092000810003602182000810003500012000040100
60204100066801045010110003200004010410003200062659991156809478914470113302092000810003602182000810003500012000040100
60204100066801045010110003200004010410003200062659991156809478914470113302092000810003602182000810003500012000040100
60204100066801045010110003200004010410003200062659991156809478914470113302092000810003602182000810003500012000040100
60204100066801045010110003200004010410003200062660612156850878933970113302092000810003602182000810003500012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0075

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60034102264801405002110099200204029410083200062660528156996879003570022300292000610003600202000010000500012000040010
60024100082800145001110003200004001010000200002660113156972678991270010300202000010000600202000010000500012000040010
60024100121800155001110004200004001410002200862667364157423379222070283301492008810043600202000010000500012000040010
60024100106800135001110002200004001010000200242662138157100779055170083300592002810013600982002610013500092000040010
60024100113800135001110002200004001010000200762667982157469579237770266301402007610040600982002810013500092000040010
60024100374800155001110004200004001410003200002661217157032679024470010300202000010000600202000010000500012000040010
60025100238800475003010011200064008110023200002660730157005079008370010300202000010000600202000010000500012000040010
60024100081800135001110002200004001010000200002660545157001479004770010300202000010000600202000010000500012000040010
60024100086800135001110002200004001010000200002660572157003279006170010300202000010000602602008010040500452000040010
60024100093800135001110002200004001010000200002660464156996079002370010300202000010000600202000010000500012000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6], #0x10
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0084

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60214102451802325011210100200204038510088200062661241156883278950870113302092000810003602182000810003500012000040100
60204100122801045010110003200004010410003200062661179156887678951970113302092000810003602182000810003500012000040100
60204100084801045010110003200004010410003200062660477156841078929670113302092000810003602182000810003500012000040100
60204100084801045010110003200004010410003200062660477156841078929670113302092000810003602182000810003500012000040100
60204100084801045010110003200004010410003200062660477156841078929670113302092000810003602182000810003500012000040100
60204100084801045010110003200004010410003200062660477156841078929670113302092000810003602182000810003500012000040100
60204100084801045010110003200004010410003200062660477156841078929670113302092000810003602182000810003500012000040100
60204100091801045010110003200004010410003200062660963156873278945270113302092000810003602182000810003500012000040100
60204100104801045010110003200004010410003200062663825157040279041870113302092000810003603382004710023500232000040100
60205101272803125022110047200444048510112200062661881156923878977070113302092000810003602182000810003500012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0076

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
600341022288013950021100982002040294100832000626600151569634789875700223002920006100036003820008100035000120000040010
600241000668001450011100032000040014100032000626600811569752789928700233002920008100036002020000100005000120000040010
600241000718001450011100032000040014100032000026603831569900790005700103002020000100006002020000100005000120000040010
600251001378002950019100082000240046100132000026603021569846789976700103002020000100006003620006100035000120000040010
600241000898001550011100042000040014100032000026604911569952790037700103002020000100006002020000100005000120000040010
600241004898008650055100152001640150100402008026688731575280792631702703014020080100406003820008100035000120000040010
600241001268001550011100042000040014100032000026613551570540790306700103002020000100006002020000100005000120000040010
600241000888001450011100032000040010100002000026602751569820789965700103002020000100006002020000100005000120000040010
600251001588002950019100082000240046100122000026608151570156790138700103002020000100006002020000100005000120000040010
600241000768001450011100032000040010100002000026603291569856789981700103002020000100006002020000100005000120000040010

Test 4: throughput

Count: 8

Code:

  ldp s0, s1, [x6], #0x10
  ldp s0, s1, [x7], #0x10
  ldp s0, s1, [x8], #0x10
  ldp s0, s1, [x9], #0x10
  ldp s0, s1, [x10], #0x10
  ldp s0, s1, [x11], #0x10
  ldp s0, s1, [x12], #0x10
  ldp s0, s1, [x13], #0x10
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0795

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160214884102406678036716030080368160008240318139331924011420016001220016001280005160000100
160204864042401058010516000080106160007240318139447124011320016001220016001280005160000100
160204863972401058010516000080106160007240318139436324011320016001220016001280005160000100
160204863952401058010516000080106160007240318139436324011320016001220016001280005160000100
160204863952401058010516000080106160007240318139436324011320016001220016001280005160000100
160204863952401058010516000080106160007240318139436324011320016001220016001280005160000100
160204863952401058010516000080106160007240318139436324011320016001220016001280005160000100
160204863952401058010516000080106160007240318139436324011320016001220016001280005160000100
160204863952401058010516000080106160007240318139436324011320016001220016006880031160000100
160204863972401058010516000080106160006240318139435024011220016001220016001280005160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0793

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
16003488554240584802840160300802850160008240048139348124002420160012201600008000116000010
16002486358240011800110160000800100160000240030139343224001020160000201600688003116000010
16002486358240011800110160000800100160007240045139454724002220160014201600008000116000010
16002486345240011800110160000800100160000240030139866324001020160000201600688003116000010
16002486366240011800110160000800100160000240030139339524001020160000201600008000116000010
16002486346240011800110160000800100160054240126138894624009620160068201600008000116000010
16002486345240011800110160000800100160000240030139339524001020160000201600008000116000010
16002486347240011800110160000800100160000240030139339524001020160000201600008000116000010
16002486345240011800110160000800100160000240030139343124001020160000201600008000116000010
16002486350240011800110160000800100160000240030139338824001020160000201600688003116000010