Icestorm: LDP (post-index, S) measurements

Code:

  ldp s0, s1, [x6], #0x10

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1937	3113	1053	2060	1052	2048	3617	26870	3074	2056	2000	1001	2000
2004	1611	3001	1001	2000	1000	2000	3522	25321	3000	2000	2056	1027	2000
2004	1555	3001	1001	2000	1000	2000	3520	24968	3000	2000	2056	1027	2000
2004	1598	3001	1001	2000	1000	2000	3520	24941	3000	2000	2000	1001	2000
2004	1596	3001	1001	2000	1000	2000	3526	24837	3000	2000	2000	1001	2000
2004	1546	3001	1001	2000	1000	2000	3520	24923	3000	2000	2000	1001	2000
2004	1587	3001	1001	2000	1000	2000	3520	25373	3000	2000	2000	1001	2000
2004	1614	3057	1027	2030	1026	2000	3520	25229	3000	2000	2000	1001	2000
2004	1552	3001	1001	2000	1000	2000	3520	25112	3000	2000	2000	1001	2000
2004	1544	3001	1001	2000	1000	2000	3520	25598	3000	2000	2000	1001	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6], #0x10
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0072

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60214	102284	80231	50112	10099	20020	40385	10089	20006	2659942	1568004	789110	70113	30209	20008	10003	60278	20028	10013	50009	20000	40100
60204	100097	80104	50101	10003	20000	40104	10002	20006	2660832	1568580	789386	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100146	80104	50101	10003	20000	40104	10003	20006	2660693	1568560	789371	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100066	80104	50101	10003	20000	40104	10003	20006	2660342	1568328	789256	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100066	80104	50101	10003	20000	40104	10003	20006	2659991	1568094	789144	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100066	80104	50101	10003	20000	40104	10003	20006	2659991	1568094	789144	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100066	80104	50101	10003	20000	40104	10003	20006	2659991	1568094	789144	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100066	80104	50101	10003	20000	40104	10003	20006	2659991	1568094	789144	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100066	80104	50101	10003	20000	40104	10003	20006	2659991	1568094	789144	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100066	80104	50101	10003	20000	40104	10003	20006	2660612	1568508	789339	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0075

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60034	102264	80140	50021	10099	20020	40294	10083	20006	2660528	1569968	790035	70022	30029	20006	10003	60020	20000	10000	50001	20000	40010
60024	100082	80014	50011	10003	20000	40010	10000	20000	2660113	1569726	789912	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100121	80015	50011	10004	20000	40014	10002	20086	2667364	1574233	792220	70283	30149	20088	10043	60020	20000	10000	50001	20000	40010
60024	100106	80013	50011	10002	20000	40010	10000	20024	2662138	1571007	790551	70083	30059	20028	10013	60098	20026	10013	50009	20000	40010
60024	100113	80013	50011	10002	20000	40010	10000	20076	2667982	1574695	792377	70266	30140	20076	10040	60098	20028	10013	50009	20000	40010
60024	100374	80015	50011	10004	20000	40014	10003	20000	2661217	1570326	790244	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60025	100238	80047	50030	10011	20006	40081	10023	20000	2660730	1570050	790083	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100081	80013	50011	10002	20000	40010	10000	20000	2660545	1570014	790047	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100086	80013	50011	10002	20000	40010	10000	20000	2660572	1570032	790061	70010	30020	20000	10000	60260	20080	10040	50045	20000	40010
60024	100093	80013	50011	10002	20000	40010	10000	20000	2660464	1569960	790023	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6], #0x10
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0084

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60214	102451	80232	50112	10100	20020	40385	10088	20006	2661241	1568832	789508	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100122	80104	50101	10003	20000	40104	10003	20006	2661179	1568876	789519	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100084	80104	50101	10003	20000	40104	10003	20006	2660477	1568410	789296	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100084	80104	50101	10003	20000	40104	10003	20006	2660477	1568410	789296	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100084	80104	50101	10003	20000	40104	10003	20006	2660477	1568410	789296	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100084	80104	50101	10003	20000	40104	10003	20006	2660477	1568410	789296	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100084	80104	50101	10003	20000	40104	10003	20006	2660477	1568410	789296	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100091	80104	50101	10003	20000	40104	10003	20006	2660963	1568732	789452	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100104	80104	50101	10003	20000	40104	10003	20006	2663825	1570402	790418	70113	30209	20008	10003	60338	20047	10023	50023	20000	40100
60205	101272	80312	50221	10047	20044	40485	10112	20006	2661881	1569238	789770	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0076

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60034	102228	80139	50021	10098	20020	40294	10083	20006	2660015	1569634	789875	70022	30029	20006	10003	60038	20008	10003	50001	20000	0	40010
60024	100066	80014	50011	10003	20000	40014	10003	20006	2660081	1569752	789928	70023	30029	20008	10003	60020	20000	10000	50001	20000	0	40010
60024	100071	80014	50011	10003	20000	40014	10003	20000	2660383	1569900	790005	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60025	100137	80029	50019	10008	20002	40046	10013	20000	2660302	1569846	789976	70010	30020	20000	10000	60036	20006	10003	50001	20000	0	40010
60024	100089	80015	50011	10004	20000	40014	10003	20000	2660491	1569952	790037	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100489	80086	50055	10015	20016	40150	10040	20080	2668873	1575280	792631	70270	30140	20080	10040	60038	20008	10003	50001	20000	0	40010
60024	100126	80015	50011	10004	20000	40014	10003	20000	2661355	1570540	790306	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100088	80014	50011	10003	20000	40010	10000	20000	2660275	1569820	789965	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60025	100158	80029	50019	10008	20002	40046	10012	20000	2660815	1570156	790138	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100076	80014	50011	10003	20000	40010	10000	20000	2660329	1569856	789981	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010

Test 4: throughput

Count: 8

Code:

  ldp s0, s1, [x6], #0x10
  ldp s0, s1, [x7], #0x10
  ldp s0, s1, [x8], #0x10
  ldp s0, s1, [x9], #0x10
  ldp s0, s1, [x10], #0x10
  ldp s0, s1, [x11], #0x10
  ldp s0, s1, [x12], #0x10
  ldp s0, s1, [x13], #0x10

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0795

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160214	88410	240667	80367	160300	80368	160008	240318	1393319	240114	200	160012	200	160012	80005	160000	100
160204	86404	240105	80105	160000	80106	160007	240318	1394471	240113	200	160012	200	160012	80005	160000	100
160204	86397	240105	80105	160000	80106	160007	240318	1394363	240113	200	160012	200	160012	80005	160000	100
160204	86395	240105	80105	160000	80106	160007	240318	1394363	240113	200	160012	200	160012	80005	160000	100
160204	86395	240105	80105	160000	80106	160007	240318	1394363	240113	200	160012	200	160012	80005	160000	100
160204	86395	240105	80105	160000	80106	160007	240318	1394363	240113	200	160012	200	160012	80005	160000	100
160204	86395	240105	80105	160000	80106	160007	240318	1394363	240113	200	160012	200	160012	80005	160000	100
160204	86395	240105	80105	160000	80106	160007	240318	1394363	240113	200	160012	200	160012	80005	160000	100
160204	86395	240105	80105	160000	80106	160007	240318	1394363	240113	200	160012	200	160068	80031	160000	100
160204	86397	240105	80105	160000	80106	160006	240318	1394350	240112	200	160012	200	160012	80005	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0793

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160034	88554	240584	80284	0	160300	80285	0	160008	240048	1393481	240024	20	160012	20	160000	80001	160000	10
160024	86358	240011	80011	0	160000	80010	0	160000	240030	1393432	240010	20	160000	20	160068	80031	160000	10
160024	86358	240011	80011	0	160000	80010	0	160007	240045	1394547	240022	20	160014	20	160000	80001	160000	10
160024	86345	240011	80011	0	160000	80010	0	160000	240030	1398663	240010	20	160000	20	160068	80031	160000	10
160024	86366	240011	80011	0	160000	80010	0	160000	240030	1393395	240010	20	160000	20	160000	80001	160000	10
160024	86346	240011	80011	0	160000	80010	0	160054	240126	1388946	240096	20	160068	20	160000	80001	160000	10
160024	86345	240011	80011	0	160000	80010	0	160000	240030	1393395	240010	20	160000	20	160000	80001	160000	10
160024	86347	240011	80011	0	160000	80010	0	160000	240030	1393395	240010	20	160000	20	160000	80001	160000	10
160024	86345	240011	80011	0	160000	80010	0	160000	240030	1393431	240010	20	160000	20	160000	80001	160000	10
160024	86350	240011	80011	0	160000	80010	0	160000	240030	1393388	240010	20	160000	20	160068	80031	160000	10

LDP (post-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations