Icestorm: LDP (pre-index, D) measurements

Code:

  ldp d0, d1, [x6, #0x10]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1839	3057	1027	2030	1026	2000	3516	25614	3000	2000	2000	1001	2000
2004	1569	3001	1001	2000	1000	2000	3516	25146	3000	2000	2000	1001	2000
2004	1559	3001	1001	2000	1000	2000	3516	25155	3000	2000	2000	1001	2000
2004	1552	3001	1001	2000	1000	2000	3516	25065	3000	2000	2000	1001	2000
2004	1539	3001	1001	2000	1000	2000	3516	25245	3000	2000	2000	1001	2000
2004	1576	3001	1001	2000	1000	2000	3516	25146	3000	2000	2000	1001	2000
2004	1558	3001	1001	2000	1000	2000	3516	25101	3000	2000	2000	1001	2000
2004	1560	3001	1001	2000	1000	2000	3516	25101	3000	2000	2000	1001	2000
2004	1582	3001	1001	2000	1000	2000	3516	24795	3000	2000	2000	1001	2000
2004	1550	3001	1001	2000	1000	2000	3516	25020	3000	2000	2000	1001	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6, #0x10]!
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0113

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60214	102453	80237	50112	10105	20020	40385	10089	20006	2660531	1568446	789313	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100084	80104	50101	10003	20000	40104	10003	20006	2660369	1568338	789263	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100080	80104	50101	10003	20000	40104	10003	20024	2662076	1569340	789761	70174	30241	20026	10013	60218	20008	10003	50001	20000	40100
60204	100080	80104	50101	10003	20000	40104	10003	20006	2660504	1568428	789303	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100088	80104	50101	10003	20000	40104	10003	20006	2660369	1568338	789263	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100080	80104	50101	10003	20000	40104	10003	20006	2660369	1568338	789263	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100080	80104	50101	10003	20000	40104	10003	20006	2660369	1568338	789263	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100080	80104	50101	10003	20000	40104	10003	20006	2660369	1568338	789263	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100080	80104	50101	10003	20000	40104	10003	20006	2660369	1568338	789263	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100080	80104	50101	10003	20000	40104	10003	20006	2660369	1568338	789263	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0066

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60034	102609	80140	50021	10099	20020	40294	10089	20006	2660069	1569670	789892	70022	30029	20006	10003	60038	20008	10003	50001	20000	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789896	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789896	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789896	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789896	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789896	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789896	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2660059	1569684	789896	70010	30020	20000	10000	60080	20020	10010	50009	20000	40010
60024	100072	80014	50011	10003	20000	40010	10000	20000	2660464	1569954	790025	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100084	80014	50011	10003	20000	40010	10000	20000	2660437	1569936	790014	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6, #0x10]!
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0117

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60214	102300	80233	50112	10101	20020	40385	10089	20006	2660428	1568320	789261	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100082	80104	50101	10003	20000	40104	10003	20006	2660018	1568118	789150	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100067	80103	50101	10002	20000	40104	10003	20006	2660018	1568118	789150	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100080	80103	50101	10002	20000	40104	10003	20006	2660477	1568424	789297	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100067	80103	50101	10002	20000	40104	10003	20006	2660018	1568118	789150	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60205	100152	80118	50109	10007	20002	40136	10013	20006	2660531	1568460	789312	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100096	80103	50101	10002	20000	40104	10003	20006	2660612	1568514	789334	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100097	80103	50101	10002	20000	40104	10003	20006	2662684	1569662	789952	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100179	80109	50101	10008	20000	40104	10003	20006	2662205	1569414	789807	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100117	80109	50101	10008	20000	40104	10003	20006	2661368	1568896	789546	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0078

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60034	102602	80135	50021	10094	20020	40294	10089	20006	2661512	1570654	790392	70023	30029	20008	10003	60038	20008	10003	50001	20000	40010
60024	100103	80014	50011	10003	20000	40014	10003	20006	2660945	1570320	790200	70023	30029	20008	10003	60020	20000	10000	50001	20000	40010
60024	100091	80014	50011	10003	20000	40010	10000	20000	2660707	1570108	790105	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100080	80014	50011	10003	20000	40010	10000	20000	2660437	1569928	790018	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100080	80014	50011	10003	20000	40010	10000	20024	2661949	1570878	790493	70083	30059	20028	10013	60020	20000	10000	50001	20000	40010
60024	100105	80014	50011	10003	20000	40010	10000	20000	2660437	1569928	790018	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100080	80014	50011	10003	20000	40010	10000	20000	2660437	1569928	790018	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100080	80014	50011	10003	20000	40010	10000	20000	2660437	1569928	790018	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100102	80014	50011	10003	20000	40010	10000	20000	2660518	1569982	790042	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100078	80014	50011	10003	20000	40010	10000	20000	2660383	1569892	790002	70010	30020	20000	10000	60098	20028	10013	50009	20000	40010

Test 4: throughput

Count: 8

Code:

  ldp d0, d1, [x6, #0x10]!
  ldp d0, d1, [x7, #0x10]!
  ldp d0, d1, [x8, #0x10]!
  ldp d0, d1, [x9, #0x10]!
  ldp d0, d1, [x10, #0x10]!
  ldp d0, d1, [x11, #0x10]!
  ldp d0, d1, [x12, #0x10]!
  ldp d0, d1, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0796

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160214	88356	240667	80367	160300	80368	160009	240318	1393717	240115	200	160012	200	160012	80005	160000	100
160204	86369	240105	80105	160000	80106	160009	240318	1393825	240115	200	160012	200	160012	80005	160000	100
160204	86366	240105	80105	160000	80106	160009	240318	1393807	240115	200	160012	200	160068	80031	160000	100
160204	86365	240105	80105	160000	80106	160008	240318	1393882	240114	200	160012	200	160012	80005	160000	100
160204	86368	240103	80103	160000	80104	160009	240318	1393915	240115	200	160012	200	160012	80005	160000	100
160204	86365	240105	80105	160000	80106	160009	240318	1393807	240115	200	160012	200	160012	80005	160000	100
160204	86366	240105	80105	160000	80106	160009	240318	1393825	240115	200	160012	200	160012	80005	160000	100
160204	86366	240105	80105	160000	80106	160009	240318	1393825	240115	200	160012	200	160012	80005	160000	100
160204	86366	240105	80105	160000	80106	160009	240318	1393825	240115	200	160012	200	160012	80005	160000	100
160205	86454	240161	80131	160030	80132	160008	240318	1393828	240114	200	160012	200	160012	80005	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0794

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160034	88299	240584	80284	160300	80285	160011	240051	1393280	240028	20	160014	20	160008	80003	160000	10
160024	86369	240011	80011	160000	80010	160000	240030	1393605	240010	20	160000	20	160000	80001	160000	10
160024	86353	240011	80011	160000	80010	160000	240030	1393533	240010	20	160000	20	160000	80001	160000	10
160024	86353	240011	80011	160000	80010	160000	240030	1393533	240010	20	160000	20	160000	80001	160000	10
160024	86353	240011	80011	160000	80010	160000	240030	1393533	240010	20	160000	20	160000	80001	160000	10
160024	86353	240011	80011	160000	80010	160000	240030	1393533	240010	20	160000	20	160064	80029	160000	10
160024	86362	240011	80011	160000	80010	160000	240030	1393533	240010	20	160000	20	160000	80001	160000	10
160024	86353	240011	80011	160000	80010	160000	240030	1393533	240010	20	160000	20	160000	80001	160000	10
160024	86353	240011	80011	160000	80010	160000	240030	1393533	240010	20	160000	20	160000	80001	160000	10
160024	86376	240011	80011	160000	80010	160000	240030	1393713	240010	20	160000	20	160000	80001	160000	10

LDP (pre-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations