Icestorm: LDP (pre-index, S) measurements

Code:

  ldp s0, s1, [x6, #0x10]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1820	3057	1027	2030	1026	2000	3516	24957	3000	2000	2000	1001	2000
2004	1546	3001	1001	2000	1000	2000	3516	24696	3000	2000	2000	1001	2000
2004	1517	3001	1001	2000	1000	2000	3516	24372	3000	2000	2000	1001	2000
2004	1510	3001	1001	2000	1000	2000	3516	24660	3000	2000	2000	1001	2000
2004	1534	3001	1001	2000	1000	2000	3516	24525	3000	2000	2000	1001	2000
2004	1534	3001	1001	2000	1000	2000	3516	24534	3000	2000	2000	1001	2000
2004	1528	3001	1001	2000	1000	2000	3516	24390	3000	2000	2000	1001	2000
2004	1507	3001	1001	2000	1000	2000	3516	24480	3000	2000	2000	1001	2000
2004	1521	3001	1001	2000	1000	2000	3516	24336	3000	2000	2000	1001	2000
2004	1532	3001	1001	2000	1000	2000	3516	24723	3000	2000	2000	1001	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6, #0x10]!
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0118

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60214	102616	80236	50112	10104	20020	40385	10089	20006	2660968	1568604	789429	70113	30209	20008	10003	60278	20025	10013	50009	20000	40100
60204	100104	80107	50101	10006	20000	40104	10003	20006	2661017	1568720	789476	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100104	80107	50101	10006	20000	40104	10003	20006	2660967	1568612	789433	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100104	80107	50101	10006	20000	40104	10003	20006	2661017	1568720	789476	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100104	80107	50101	10006	20000	40104	10003	20006	2661017	1568720	789476	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100109	80107	50101	10006	20000	40104	10003	20006	2661017	1568720	789476	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100104	80107	50101	10006	20000	40104	10003	20006	2661017	1568720	789476	70113	30209	20008	10003	60278	20028	10013	50009	20000	40100
60204	100108	80107	50101	10006	20000	40104	10002	20006	2661125	1568792	789511	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100122	80107	50101	10006	20000	40104	10003	20024	2663533	1570282	790248	70173	30239	20028	10013	60218	20008	10003	50001	20000	40100
60204	100188	80107	50101	10006	20000	40104	10003	20006	2661017	1568720	789476	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0119

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60034	102465	80143	50021	10102	20020	40294	10089	20024	2662305	1571030	790603	70083	30059	20028	10013	60038	20008	10003	50001	20000	40010
60024	100086	80014	50011	10003	20000	40010	10000	20000	2660194	1569780	789935	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100081	80013	50011	10002	20000	40010	10000	20000	2660194	1569780	789935	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100071	80013	50011	10002	20000	40010	10000	20000	2660194	1569780	789935	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100071	80013	50011	10002	20000	40010	10000	20000	2660194	1569780	789935	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100071	80013	50011	10002	20000	40010	10000	20000	2660194	1569780	789935	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100071	80013	50011	10002	20000	40010	10000	20000	2660194	1569780	789935	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100071	80013	50011	10002	20000	40010	10000	20000	2660194	1569780	789935	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60025	100146	80028	50019	10007	20002	40046	10013	20000	2660248	1569816	789953	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010
60024	100071	80013	50011	10002	20000	40010	10000	20000	2660194	1569780	789935	70010	30020	20000	10000	60020	20000	10000	50001	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6, #0x10]!
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0080

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60214	102243	80230	50112	10098	20020	40385	10089	20006	2660531	1568446	789313	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100080	80104	50101	10003	20000	40104	10003	20006	2660126	1568190	789182	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100071	80103	50101	10002	20000	40104	10003	20006	2660126	1568190	789182	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100071	80103	50101	10002	20000	40104	10003	20006	2660126	1568190	789182	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60205	100199	80118	50109	10007	20002	40136	10013	20006	2660693	1568568	789362	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100071	80103	50101	10002	20000	40104	10003	20006	2660126	1568190	789182	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100071	80103	50101	10002	20000	40104	10003	20006	2660126	1568190	789182	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100071	80103	50101	10002	20000	40104	10003	20006	2660126	1568190	789182	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100071	80103	50101	10002	20000	40104	10003	20006	2660126	1568190	789182	70113	30209	20008	10003	60218	20008	10003	50001	20000	40100
60204	100071	80103	50101	10002	20000	40104	10003	20006	2660126	1568190	789182	70113	30209	20008	10003	60278	20028	10013	50009	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0079

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60034	102453	80141	50021	10100	20020	40294	10089	20006	2660081	1569752	789927	70023	30029	20008	10003	60020	20000	10000	50001	20000	0	40010
60025	100130	80028	50019	10007	20002	40046	10012	20000	2659870	1569572	789833	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100059	80013	50011	10002	20000	40010	10000	20000	2659870	1569572	789833	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100059	80013	50011	10002	20000	40010	10000	20000	2659870	1569572	789833	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100059	80013	50011	10002	20000	40010	10000	20000	2659870	1569572	789833	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100059	80013	50011	10002	20000	40010	10000	20000	2659870	1569572	789833	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100059	80013	50011	10002	20000	40010	10000	20000	2659870	1569572	789833	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100059	80013	50011	10002	20000	40010	10000	20000	2659870	1569572	789833	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010
60024	100059	80013	50011	10002	20000	40010	10000	20000	2659870	1569572	789833	70010	30020	20000	10000	60098	20028	10013	50009	20000	0	40010
60024	100066	80014	50011	10003	20000	40010	10000	20000	2659870	1569572	789833	70010	30020	20000	10000	60020	20000	10000	50001	20000	0	40010

Test 4: throughput

Count: 8

Code:

  ldp s0, s1, [x6, #0x10]!
  ldp s0, s1, [x7, #0x10]!
  ldp s0, s1, [x8, #0x10]!
  ldp s0, s1, [x9, #0x10]!
  ldp s0, s1, [x10, #0x10]!
  ldp s0, s1, [x11, #0x10]!
  ldp s0, s1, [x12, #0x10]!
  ldp s0, s1, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0794

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160214	88538	240665	80365	160300	80366	160005	240312	1392530	240109	200	160008	200	160008	80003	160000	100
160204	86362	240103	80103	160000	80104	160004	240312	1393500	240108	200	160008	200	160008	80003	160000	100
160204	86377	240103	80103	160000	80104	160004	240312	1392903	240108	200	160008	200	160008	80003	160000	100
160204	86351	240103	80103	160000	80104	160004	240312	1393446	240108	200	160008	200	160008	80003	160000	100
160205	86372	240103	80103	160000	80104	160005	240312	1393697	240109	200	160008	200	160008	80003	160000	100
160204	86348	240103	80103	160000	80104	160004	240312	1393446	240108	200	160008	200	160008	80003	160000	100
160204	86354	240103	80103	160000	80104	160005	240312	1393459	240109	200	160008	200	160008	80003	160000	100
160204	86348	240103	80103	160000	80104	160004	240312	1393446	240108	200	160008	200	160008	80003	160000	100
160204	86348	240103	80103	160000	80104	160004	240312	1393446	240108	200	160008	200	160008	80003	160000	100
160204	86348	240103	80103	160000	80104	160004	240312	1393446	240108	200	160008	200	160008	80003	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0793

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160034	88709	240585	80285	160300	80286	160010	240051	1393210	240027	20	160014	20	160000	80001	160000	10
160024	86357	240011	80011	160000	80010	160000	240030	1393443	240010	20	160000	20	160000	80001	160000	10
160024	86358	240011	80011	160000	80010	160000	240030	1393425	240010	20	160000	20	160000	80001	160000	10
160024	86806	240235	80115	160120	80114	160000	240030	1393470	240010	20	160000	20	160000	80001	160000	10
160024	86347	240011	80011	160000	80010	160000	240030	1393425	240010	20	160000	20	160000	80001	160000	10
160024	86347	240011	80011	160000	80010	160000	240030	1393425	240010	20	160000	20	160000	80001	160000	10
160024	86347	240011	80011	160000	80010	160000	240030	1393425	240010	20	160000	20	160000	80001	160000	10
160024	86347	240011	80011	160000	80010	160000	240030	1393425	240010	20	160000	20	160000	80001	160000	10
160024	86347	240011	80011	160000	80010	160000	240030	1393425	240010	20	160000	20	160000	80001	160000	10
160024	86347	240011	80011	160000	80010	160000	240030	1393425	240010	20	160000	20	160000	80001	160000	10

LDP (pre-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations