Icestorm: LDP (signed offset, D) measurements

Code:

  ldp d0, d1, [x6, #0x10]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
11756	75856	10717	4907	28	5782	4727	30	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	0	2000	0	0	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	0	2000	0	0	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	0	2000	0	0	2000	18360	2000	2000	2000	1	2000
2004	1054	2001	1	0	2000	0	0	2000	16290	2000	2000	2000	1	2000
2004	1054	2001	1	0	2000	0	0	2000	16218	2000	2000	2000	1	2000
2004	1054	2001	1	0	2000	0	0	2000	16218	2000	2000	2000	1	2000
2004	1056	2001	1	0	2000	0	0	2000	16272	2000	2000	2000	1	2000
2004	1054	2001	1	0	2000	0	0	2000	16272	2000	2000	2000	1	2000
2004	1058	2001	1	0	2000	0	0	2000	16218	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6, #0x10]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100149	70109	40101	10006	20002	30130	10015	20004	2669253	1779454	1093142	60110	30211	20008	10004	60224	20008	10004	40001	20000	40100
60204	100051	70103	40101	10002	20000	30103	10003	20004	2669226	1779436	1093131	60110	30211	20008	10004	60222	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669226	1779436	1093131	60110	30211	20008	10004	60222	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669226	1779436	1093131	60110	30211	20008	10004	60222	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669226	1779436	1093131	60110	30211	20008	10004	60222	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669226	1779436	1093131	60110	30211	20008	10004	60222	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669226	1779436	1093131	60110	30211	20008	10004	60222	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669226	1779436	1093131	60110	30211	20008	10004	60222	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669226	1779436	1093131	60110	30211	20008	10004	60222	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669226	1779436	1093131	60110	30211	20008	10004	60288	20028	10015	40008	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	100156	70019	40011	10006	20002	30040	10015	20004	2669217	1779326	1049469	60020	30032	20008	10004	60044	20008	10004	40001	20000	0	40010
60024	100047	70013	40011	10002	20000	30013	10003	20004	2669080	1779274	1049460	60020	30032	20008	10004	60044	20008	10004	40001	20000	0	40010
60024	100040	70012	40011	10001	20000	30013	10003	20004	2669080	1779274	1049460	60020	30032	20008	10004	60044	20008	10004	40001	20000	0	40010
60024	100040	70012	40011	10001	20000	30013	10003	20004	2669080	1779274	1049460	60020	30032	20008	10004	60044	20008	10004	40001	20000	0	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100040	70012	40011	10001	20000	30010	10000	20024	2669437	1779502	1049562	60082	30065	20028	10015	60020	20000	10000	40001	20000	0	40010
60024	100040	70012	40011	10001	20000	30010	10000	20000	2669060	1779230	1049412	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp d0, d1, [x6, #0x10]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100156	70109	40101	10006	20002	30130	10015	20004	2669141	1779300	1048443	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60286	20028	10015	40008	20000	40100
60204	100055	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100051	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100153	70019	40011	10006	20002	30040	10015	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60044	20008	10004	40001	20000	40010
60024	100247	70045	40029	10008	20008	30074	10022	20000	2669303	1779392	1049511	60010	30020	20000	10000	60148	20040	10022	40019	20000	40010
60024	100808	70044	40028	10008	20008	30075	10022	20000	2669411	1779464	1049555	60010	30020	20000	10000	60152	20040	10022	40019	20000	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669276	1779374	1049500	60010	30020	20000	10000	61104	20341	10186	40151	20000	40010
60024	102762	70334	40192	10062	20080	30653	10220	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20024	2671300	1780744	1050318	60082	30065	20028	10015	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 4: throughput

Count: 8

Code:

  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]
  ldp d0, d1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80164	160131	101	160030	100	160056	300	496512	160156	200	160068	200	160012	1	160000	100
160204	80067	160105	101	160004	100	160008	300	1280194	160108	200	160012	200	160012	1	160000	100
160204	80141	160101	101	160000	100	160106	307	1190874	160208	202	160128	200	160012	1	160000	100
160204	80493	160221	101	160120	100	160008	300	1280194	160108	200	160012	200	160012	1	160000	100
160204	80053	160101	101	160000	100	160008	300	1280194	160108	200	160012	200	160012	1	160000	100
160204	80053	160101	101	160000	100	160008	300	1280194	160108	200	160012	200	160012	1	160000	100
160204	80053	160101	101	160000	100	160008	300	1280194	160108	200	160012	200	160012	1	160000	100
160204	80053	160101	101	160000	100	160056	300	694402	160156	200	160068	200	160012	1	160000	100
160204	80053	160101	101	160000	100	160008	300	1280194	160108	200	160012	200	160012	1	160000	100
160204	80053	160101	101	160000	100	160056	300	749672	160156	200	160068	200	160012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80191	160045	11	160034	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280506	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280380	160010	20	160000	20	160068	1	160000	10
160025	80111	160045	11	160034	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10
160024	80054	160011	11	160000	10	160000	30	1280362	160010	20	160000	20	160000	1	160000	10
160024	80059	160011	11	160000	10	160000	30	1280218	160010	20	160000	20	160000	1	160000	10

LDP (signed offset, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations