Icestorm: LDP (signed offset, Q) measurements

Code:

  ldp q0, q1, [x6, #0x10]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1169	2031	1	2030	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000
2004	1052	2001	1	2000	2000	16173	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp q0, q1, [x6, #0x10]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100262	70109	40101	10006	20002	30130	10015	20004	2669138	1779298	1048442	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
78854	163018	87061	51390	9238	26433	42748	9277	20004	2669287	1779472	1048592	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60205	100082	70114	40108	10004	20002	30134	10014	20004	2669044	1779310	1048493	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100148	70019	40011	10006	20002	30040	10015	20004	2669283	1779374	1049499	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60025	100080	70024	40018	10004	20002	30044	10014	20004	2669269	1779400	1049537	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30013	10003	20004	2669269	1779400	1049537	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30013	10003	20004	2669269	1779400	1049537	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30013	10003	20004	2669269	1779400	1049537	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30013	10003	20004	2669350	1779454	1049570	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30013	10003	20004	2669269	1779400	1049537	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100049	70013	40011	10002	20000	30013	10003	20004	2669269	1779400	1049537	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30013	10003	20024	2669626	1779628	1049639	60082	30065	20028	10015	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30013	10003	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp q0, q1, [x6, #0x10]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0043

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100158	70109	40101	10006	20002	30130	10015	20004	2669168	1779318	1048454	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100052	70103	40101	10002	20000	30103	10003	20004	2669071	1779328	1048504	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100043	70102	40101	10001	20000	30103	10003	20004	2669071	1779328	1048504	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100043	70102	40101	10001	20000	30103	10003	20004	2669071	1779328	1048504	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100043	70102	40101	10001	20000	30103	10003	20004	2669071	1779328	1048504	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60205	100076	70113	40108	10003	20002	30134	10014	20004	2669557	1779652	1048702	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100043	70102	40101	10001	20000	30103	10003	20004	2669071	1779328	1048504	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100043	70102	40101	10001	20000	30103	10003	20004	2669071	1779328	1048504	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100043	70102	40101	10001	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100052	70102	40101	10001	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0041

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100154	70019	40011	10006	20002	30040	10015	20004	2669055	1779218	1049403	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100043	70012	40011	10001	20000	30010	10000	20020	2670581	1780236	1049990	60072	30053	20020	10011	60020	20000	10000	40001	20000	40010
60024	100048	70013	40011	10002	20000	30013	10003	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100041	70012	40011	10001	20000	30010	10000	20024	2670763	1780388	1050105	60082	30061	20028	10015	60020	20000	10000	40001	20000	40010
60024	100041	70012	40011	10001	20000	30010	10000	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100041	70012	40011	10001	20000	30010	10000	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100046	70012	40011	10001	20000	30010	10000	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60025	103001	70023	40018	10003	20002	30044	10014	20000	2669222	1779338	1049478	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100041	70012	40011	10001	20000	30010	10000	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100041	70012	40011	10001	20000	30010	10000	20000	2669087	1779248	1049423	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 4: throughput

Count: 8

Code:

  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]
  ldp q0, q1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80352	160137	101	160036	100	160008	300	496260	0	160108	200	160012	0	200	160012	1	160000	100
160204	80057	160101	101	160000	100	160009	300	1280036	0	160109	200	160012	0	200	160124	1	160000	100
160205	80103	160137	101	160036	100	160009	300	1280036	0	160109	200	160012	0	200	160012	1	160000	100
160204	80422	160135	101	160034	100	160009	300	1280036	0	160109	200	160012	0	200	160012	1	160000	100
160204	80051	160101	101	160000	100	160056	300	813777	0	160156	200	160068	0	200	160012	1	160000	100
160204	80048	160101	101	160000	100	160009	300	1280036	0	160109	200	160012	0	200	160068	1	160000	100
160204	80048	160101	101	160000	100	160009	300	1280036	0	160109	200	160012	0	200	160012	1	160000	100
160204	80539	160165	101	160064	100	160009	300	1280036	0	160109	200	160012	0	200	160012	1	160000	100
160204	80656	160195	101	160094	100	160152	307	533439	0	160254	202	160182	0	200	160012	1	160000	100
160204	80048	160101	101	160000	100	160009	300	1280036	0	160109	200	160012	0	200	160068	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80187	160045	11	160034	10	160000	30	1280803	160010	20	160000	20	160000	1	160000	10
160024	80052	160011	11	160000	10	160000	30	1280173	160010	20	160000	20	160000	1	160000	10
160024	80052	160011	11	160000	10	160000	30	1280173	160010	20	160000	20	160000	1	160000	10
160024	80052	160011	11	160000	10	160000	30	1280173	160010	20	160000	20	160000	1	160000	10
160024	80052	160011	11	160000	10	160000	30	1280173	160010	20	160000	20	160000	1	160000	10
160024	80052	160011	11	160000	10	160000	30	1280173	160010	20	160000	20	160000	1	160000	10
160024	80052	160011	11	160000	10	160000	30	1280173	160010	20	160000	20	160000	1	160000	10
160025	80151	160041	11	160030	10	160000	30	1280497	160010	20	160000	20	160000	1	160000	10
160024	80052	160011	11	160000	10	160000	30	1280173	160010	20	160000	20	160000	1	160000	10
160024	80052	160011	11	160000	10	160000	30	1280173	160010	20	160000	20	160000	1	160000	10

LDP (signed offset, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations