Icestorm: LDP (signed offset, S) measurements

Code:

  ldp s0, s1, [x6, #0x10]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
2005	1156	2031	1	2030	2000	16480	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16272	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1054	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000
2004	1051	2001	1	2000	2000	16164	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6, #0x10]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100156	70109	40101	10006	20002	30130	10015	20004	2669193	1779374	1048510	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100069	70104	40101	10003	20000	30103	10003	20024	2669579	1779582	1048586	60172	30245	20028	10015	60224	20008	10004	40001	20000	40100
60204	100066	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60290	20028	10015	40008	20000	40100
65002	116104	73949	42421	10059	21469	32289	10067	20004	2669341	1779508	1048614	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60205	100090	70115	40108	10005	20002	30134	10014	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100149	70019	40011	10006	20002	30040	10015	20004	2669230	1779374	1049518	60020	30032	20008	10004	60044	20008	10004	40001	20000	40010
60024	100044	70012	40011	10001	20000	30010	10000	20000	2669168	1779302	1049456	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60025	100075	70023	40018	10003	20002	30044	10014	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ldp s0, s1, [x6, #0x10]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100156	70109	40101	10006	20002	30130	10015	20004	2669102	1779270	1048424	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60205	100092	70115	40108	10005	20002	30134	10014	20004	2669328	1779464	1048565	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100154	70103	40101	10002	20000	30103	10003	20026	2670096	1780006	1048882	60172	30240	20030	10014	60282	20028	10015	40008	20000	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60205	100073	70113	40108	10003	20002	30134	10014	20004	2669476	1779598	1048669	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100040	70102	40101	10001	20000	30103	10003	20004	2668990	1779274	1048471	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60205	102129	70114	40108	10004	20002	30134	10014	20004	2669719	1779760	1048766	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60206	100116	70125	40115	10006	20004	30165	10025	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100158	70019	40011	10006	20002	30040	10015	20004	2669229	1779340	1049477	60020	30032	20008	10004	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100057	70013	40011	10002	20000	30010	10000	20000	2669384	1779446	1049544	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100053	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20024	2669629	1779632	1049640	60082	30061	20028	10015	60020	20000	10000	40001	20000	40010
60025	100136	70025	40018	10005	20002	30044	10014	20000	2669330	1779410	1049522	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 4: throughput

Count: 8

Code:

  ldp s0, s1, [x6, #0x10]
  ldp s0, s1, [x6, #0x10]
  ldp s0, s1, [x6, #0x10]
  ldp s0, s1, [x6, #0x10]
  ldp s0, s1, [x6, #0x10]
  ldp s0, s1, [x6, #0x10]
  ldp s0, s1, [x6, #0x10]
  ldp s0, s1, [x6, #0x10]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80172	160135	101	160034	100	160008	300	672242	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280316	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160068	1	160000	100
160204	80116	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280244	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160056	307	1008508	160158	202	160070	200	160012	1	160000	100
160446	82746	160424	237	160187	217	160010	300	966180	160110	200	160014	200	160012	1	160000	100
160204	80049	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100
160204	80047	160101	101	160000	100	160008	300	1280028	160108	200	160012	200	160012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80196	160041	11	160030	10	160008	30	800296	0	160018	20	160012	0	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160056	30	1273032	0	160066	20	160068	0	20	160000	1	160000	10
160024	80052	160011	11	160000	10	160000	30	1280164	0	160010	20	160000	0	20	160000	1	160000	10
160024	80052	160011	11	160000	10	160000	30	1280218	0	160010	20	160000	0	20	160000	1	160000	10
160025	80294	160041	11	160030	10	160000	30	1280380	0	160010	20	160000	0	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	0	160010	20	160000	0	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	0	160010	20	160000	0	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	0	160010	20	160000	0	20	160000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	1280164	0	160010	20	160000	0	20	160000	1	160000	10
160025	80105	160045	11	160034	10	160000	30	1280272	0	160010	20	160000	0	20	160000	1	160000	10

LDP (signed offset, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations