Icestorm: LDR (D) measurements

Code:

  ldr d0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	667	1031	1	1030	1000	8164	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7990	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50204	100047	60103	40101	10002	10000	30103	10003	10004	2668978	1045465	1070645	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669077	1045565	1070737	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100041	60102	40101	10001	10000	30103	10003	10016	2671246	1046438	1071600	50164	30246	10017	10016	60376	10028	10030	40013	10000	40100
50205	100092	60112	40107	10004	10001	30133	10015	10004	2668985	1045408	1070594	50110	30212	10004	10004	60300	10017	10017	40007	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100044	60102	40101	10001	10000	30103	10003	10004	2672101	1046848	1071983	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10015	2669444	1046429	1070914	50164	30250	10017	10017	60224	10004	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100146	60018	40011	10006	10001	30040	10014	10004	2669257	1046891	1071937	50020	30032	10004	10004	60020	10000	10000	40001	10000	40010
50025	100077	60021	40015	10004	10002	30043	10015	10000	2669552	1047027	1072064	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10015	2669666	1047095	1072139	50074	30070	10017	10017	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100057	60013	40011	10002	10000	30010	10000	10014	2669666	1047093	1072125	50072	30067	10016	10017	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010

Test 3: throughput

Count: 8

Code:

  ldr d0, [x6]
  ldr d0, [x6]
  ldr d0, [x6]
  ldr d0, [x6]
  ldr d0, [x6]
  ldr d0, [x6]
  ldr d0, [x6]
  ldr d0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40164	80135	101	80034	100	80008	300	483840	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40069	80101	101	80000	100	80059	300	436287	80159	200	80071	200	80012	1	80000	100
80204	40064	80105	101	80004	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40062	80101	101	80000	100	80008	300	640302	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40264	80045	11	80034	10	80008	30	400188	80018	20	80012	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80069	1	80000	10

LDR (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations