Icestorm: LDR (Q) measurements

Code:

  ldr q0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	647	1031	1	1030	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	553	1001	1	1000	1000	8236	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	557	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8344	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50205	100152	60108	40101	10006	10001	30130	10014	10004	2669212	1045618	1070792	50110	30212	10004	10004	60294	10017	10016	40005	10000	0	40100
50204	100061	60103	40101	10002	10000	30103	10003	10016	2672028	1046762	1071972	50164	30250	10017	10017	60224	10004	10004	40001	10000	0	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100152	60116	40109	10005	10002	30136	10016	10004	2669212	1045618	1070792	50110	30212	10004	10004	60294	10016	10017	40007	10000	0	40100
50204	100060	60103	40101	10002	10000	30103	10003	10016	2671037	1046370	1071534	50164	30251	10016	10017	60224	10004	10004	40001	10000	0	40100
50204	100148	60116	40109	10005	10002	30136	10016	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669374	1045685	1070859	50110	30212	10004	10004	60294	10015	10016	40009	10000	0	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100056	60103	40101	10002	10000	30103	10003	10016	2671521	1046592	1071782	50169	30250	10017	10017	60224	10004	10004	40001	10000	0	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100152	60018	40011	10006	10001	30040	10014	10004	2669383	1047000	1072040	50020	30032	10004	10004	60020	10000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100056	60013	40011	10002	10000	30010	10000	10014	2669750	1047129	1072161	50072	30067	10016	10017	60020	10000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100053	60013	40011	10002	10000	30010	10000	10003	2669299	1046855	1071902	50019	30030	10004	10004	60044	10004	10004	40001	10000	40010
50024	100074	60014	40011	10003	10000	30010	10000	10000	2671388	1047771	1072808	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100050	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010

Test 3: throughput

Count: 8

Code:

  ldr q0, [x6]
  ldr q0, [x6]
  ldr q0, [x6]
  ldr q0, [x6]
  ldr q0, [x6]
  ldr q0, [x6]
  ldr q0, [x6]
  ldr q0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40187	80135	101	80034	100	80008	300	455196	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40354	80045	11	80034	10	80008	30	640248	80018	20	80012	20	80012	1	80000	10
80024	40058	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40060	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640326	80010	20	80000	20	80000	1	80000	10
80024	40063	80011	11	80000	10	80000	30	640434	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80071	1	80000	10
80024	40066	80011	11	80000	10	80000	30	640362	80010	20	80000	20	80000	1	80000	10
80024	40072	80011	11	80000	10	80000	30	640272	80010	20	80000	20	80000	1	80000	10
80024	40063	80011	11	80000	10	80000	30	640380	80010	20	80000	20	80000	1	80000	10
80024	40063	80011	11	80000	10	80000	30	640380	80010	20	80000	20	80000	1	80000	10

LDR (Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations