Icestorm: LDR (S) measurements

Code:

  ldr s0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	659	1031	1	1030	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0044

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50205	100157	60108	40101	10006	10001	30130	10014	10004	2669491	1045681	1070859	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100051	60103	40101	10002	10000	30103	10003	10004	2669185	1045611	1070781	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100045	60102	40101	10001	10000	30103	10003	10004	2669104	1045575	1070749	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100044	60102	40101	10001	10000	30103	10003	10004	2669185	1045608	1070781	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50205	100160	60110	40105	10003	10002	30133	10015	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100044	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100044	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	1355770	884230	15208	614657	466209	3852	742601

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100892	60070	40043	10016	10011	30166	10064	10004	2669258	1046891	1071937	50020	30032	10004	10004	60120	10017	10017	40005	10000	40010
50025	100096	60023	40015	10006	10002	30043	10015	10000	2669318	1046873	1071916	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100056	60012	40011	10001	10000	30010	10000	10049	2675864	1049598	1074645	50243	30172	10049	10052	60020	10000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100056	60012	40011	10001	10000	30010	10000	10050	2675843	1049587	1074742	50240	30176	10050	10052	60020	10000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100426	60064	40043	10012	10009	30139	10051	10000	2669849	1047154	1072188	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50025	100082	60022	40017	10004	10001	30043	10016	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010

Test 3: throughput

Count: 8

Code:

  ldr s0, [x6]
  ldr s0, [x6]
  ldr s0, [x6]
  ldr s0, [x6]
  ldr s0, [x6]
  ldr s0, [x6]
  ldr s0, [x6]
  ldr s0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40336	80131	101	80030	100	80008	300	280188	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40051	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40048	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80072	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40048	80101	101	80000	100	80008	300	640356	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40249	80047	11	80036	10	80000	30	319982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10

LDR (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations