Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (literal, D)

Test 1: uops

Code:

  ldr d0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	? int output thing (e9)	? ldst retires (ed)
1004	985	1001	1	1000	1000	10138	1000	1000	1	1000
1004	715	1001	1	1000	1000	10714	1000	1000	1	1000
1004	699	1001	1	1000	1000	10588	1000	1000	1	1000
1004	706	1001	1	1000	1000	10734	1000	1000	1	1000
1004	700	1001	1	1000	1000	10760	1000	1000	1	1000
1004	715	1001	1	1000	1000	10840	1000	1000	1	1000
1004	701	1001	1	1000	1000	10625	1000	1000	1	1000
1004	698	1001	1	1000	1000	10761	1000	1000	1	1000
1004	696	1001	1	1000	1000	10788	1000	1000	1	1000
1004	692	1001	1	1000	1000	10698	1000	1000	1	1000

Test 2: throughput

Count: 8

Code:

  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4
  ldr d0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5023

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80204	40462	80105	101	80004	100	80155	300	351539	80255	200	80186	200	1	80000	100
80204	40168	80107	101	80006	100	80008	300	247111	80108	200	80012	200	1	80000	100
80204	40268	80101	101	80000	100	80010	300	641153	80110	200	80014	200	1	80000	100
80204	40157	80101	101	80000	100	80059	300	355996	80159	200	80072	200	1	80000	100
80204	40153	80101	101	80000	100	80008	300	642828	80108	200	80012	200	1	80000	100
80204	40195	80101	101	80000	100	80008	300	642640	80108	200	80012	200	1	80000	100
80204	40137	80101	101	80000	100	80008	300	643666	80108	200	80012	200	1	80000	100
80204	40194	80101	101	80000	100	80008	300	642604	80108	200	80012	200	1	80000	100
80204	40261	80131	101	80030	100	80008	300	641830	80108	200	80012	200	1	80000	100
80204	40149	80101	101	80000	100	80008	300	642694	80108	200	80012	200	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5202

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80024	43640	80011	11	80000	10	80000	30	665556	80010	20	80000	20	1	80000	10
80024	41725	80011	11	80000	10	80000	30	667341	80010	20	80000	20	1	80000	10
80024	41622	80011	11	80000	10	80000	30	667576	80010	20	80000	20	1	80000	10
80025	41726	80041	11	80030	10	80000	30	667165	80010	20	80000	20	1	80000	10
80024	41608	80011	11	80000	10	80000	30	667239	80010	20	80000	20	1	80000	10
80024	41604	80011	11	80000	10	80000	30	667548	80010	20	80000	20	1	80000	10
80024	41620	80011	11	80000	10	80000	30	667108	80010	20	80000	20	1	80000	10
80024	41605	80011	11	80000	10	80000	30	667927	80010	20	80000	20	1	80000	10
80024	41607	80011	11	80000	10	80000	30	667748	80010	20	80000	20	1	80000	10
80024	41591	80011	11	80000	10	80000	30	667635	80010	20	80000	20	1	80000	10