Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (literal, Q)

Test 1: uops

Code:

  ldr q0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	? int output thing (e9)	? ldst retires (ed)
1004	975	1001	1	1000	1000	10884	1000	1000	1	1000
1004	700	1001	1	1000	1000	10664	1000	1000	1	1000
1004	685	1001	1	1000	1000	10646	1000	1000	1	1000
1004	680	1001	1	1000	1000	10439	1000	1000	1	1000
1004	685	1001	1	1000	1000	10682	1000	1000	1	1000
1004	685	1001	1	1000	1000	10574	1000	1000	1	1000
1004	690	1001	1	1000	1000	10475	1000	1000	1	1000
1004	677	1001	1	1000	1000	10574	1000	1000	1	1000
1004	682	1001	1	1000	1000	10439	1000	1000	1	1000
1004	686	1001	1	1000	1000	10574	1000	1000	1	1000

Test 2: throughput

Count: 8

Code:

  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4
  ldr q0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5023

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80204	40410	80101	101	0	80000	100	0	80010	300	254066	80110	200	80014	200	0	1	80000	100
80204	40156	80101	101	0	80000	100	0	80060	300	642032	80160	200	80072	200	0	1	80000	100
80204	40154	80108	101	0	80007	100	0	80008	300	642552	80108	200	80012	200	0	1	80000	100
80204	40140	80101	101	0	80000	100	0	80008	300	642678	80108	200	80012	200	0	1	80000	100
80204	40176	80101	101	0	80000	100	0	80008	300	642606	80108	200	80012	200	0	1	80000	100
80204	40144	80101	101	0	80000	100	0	80008	300	642534	80108	200	80012	200	0	1	80000	100
80204	40183	80101	101	0	80000	100	0	80008	300	642408	80108	200	80012	200	0	1	80000	100
80204	40178	80101	101	0	80000	100	0	80008	300	642516	80108	200	80012	200	0	1	80000	100
80204	40137	80101	101	0	80000	100	0	80008	300	642696	80108	200	80012	200	0	1	80000	100
80204	40193	80101	101	0	80000	100	0	80008	300	642516	80108	200	80012	200	0	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5279

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	44683	80041	11	80030	10	80203	30	668746	80213	20	80242	20	1	80000	10
80024	42266	80011	11	80000	10	80000	30	678672	80010	20	80000	20	1	80000	10
80024	42228	80011	11	80000	10	80000	30	679152	80010	20	80000	20	1	80000	10
80024	42216	80011	11	80000	10	80000	30	678928	80010	20	80000	20	1	80000	10
80024	42208	80011	11	80000	10	80000	30	678508	80010	20	80000	20	1	80000	10
80024	42235	80011	11	80000	10	80000	30	678726	80010	20	80000	20	1	80000	10
80024	42225	80011	11	80000	10	80000	30	678902	80010	20	80000	20	1	80000	10
80024	42216	80011	11	80000	10	80000	30	678857	80010	20	80000	20	1	80000	10
80024	42202	80011	11	80000	10	80000	30	678849	80010	20	80000	20	1	80000	10
80024	42216	80011	11	80000	10	80059	30	664016	80069	20	80072	20	1	80000	10