Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (literal, S)

Test 1: uops

Code:

  ldr s0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	? int output thing (e9)	? ldst retires (ed)
1004	918	1001	1	1000	1000	10805	1000	1000	1	1000
1004	702	1001	1	1000	1000	10955	1000	1000	1	1000
1004	692	1001	1	1000	1000	10845	1000	1000	1	1000
1004	694	1001	1	1000	1000	10718	1000	1000	1	1000
1004	696	1001	1	1000	1000	10745	1000	1000	1	1000
1004	694	1001	1	1000	1000	10747	1000	1000	1	1000
1004	688	1001	1	1000	1000	10736	1000	1000	1	1000
1004	695	1001	1	1000	1000	10783	1000	1000	1	1000
1004	697	1001	1	1000	1000	10657	1000	1000	1	1000
1004	689	1001	1	1000	1000	10709	1000	1000	1	1000

Test 2: throughput

Count: 8

Code:

  ldr s0, .+4
  ldr s0, .+4
  ldr s0, .+4
  ldr s0, .+4
  ldr s0, .+4
  ldr s0, .+4
  ldr s0, .+4
  ldr s0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5024

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80204	40391	80101	101	80000	100	80011	300	643030	80111	200	80015	200	1	80000	100
80204	40224	80107	101	80006	100	80008	300	641954	80108	200	80012	200	1	80000	100
80204	40191	80101	101	80000	100	80009	300	641789	80109	200	80012	200	1	80000	100
80204	40196	80101	101	80000	100	80008	300	641666	80108	200	80012	200	1	80000	100
80204	40191	80101	101	80000	100	80008	300	641738	80108	200	80012	200	1	80000	100
80204	40212	80101	101	80000	100	80009	300	642635	80109	200	80012	200	1	80000	100
80204	40200	80101	101	80000	100	80009	300	641717	80109	200	80012	200	1	80000	100
80204	40193	80101	101	80000	100	80008	300	641810	80108	200	80012	200	1	80000	100
80204	40148	80101	101	80000	100	80059	300	642852	80159	200	80072	200	1	80000	100
80204	40195	80101	101	80000	100	80008	300	641846	80108	200	80012	200	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5158

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80024	43336	80017	11	80006	10	80000	30	292410	80010	20	80000	20	1	80000	10
80024	41325	80011	11	80000	10	80192	37	376536	80204	22	80226	20	1	80000	10
80024	41266	80011	11	80000	10	80000	30	661310	80010	20	80000	20	1	80000	10
80024	41267	80011	11	80000	10	80048	30	604945	80058	20	80057	20	1	80000	10
80024	41266	80011	11	80000	10	80000	30	661369	80010	20	80000	20	1	80000	10
80024	41259	80011	11	80000	10	80000	30	661256	80010	20	80000	20	1	80000	10
80024	41251	80011	11	80000	10	80000	30	661360	80010	20	80000	20	1	80000	10
80024	41251	80011	11	80000	10	80000	30	660974	80010	20	80000	20	1	80000	10
80024	41258	80011	11	80000	10	80048	30	604664	80058	20	80057	20	1	80000	10
80024	41455	80071	11	80060	10	80000	30	661112	80010	20	80000	20	1	80000	10