Icestorm: LDR (post-index, D) measurements

Code:

  ldr d0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1229	2076	1046	1030	1052	1000	17977	16963	2000	1000	1000	1001	1000
1004	1039	2001	1001	1000	1000	1000	18065	16815	2000	1000	1000	1001	1000
1004	1033	2001	1001	1000	1000	1000	18189	17141	2000	1000	1000	1001	1000
1004	1037	2001	1001	1000	1000	1000	18305	16815	2000	1000	1000	1001	1000
1004	1038	2001	1001	1000	1000	1000	18413	16819	2000	1000	1000	1001	1000
1004	1050	2001	1001	1000	1000	1000	17949	16903	2000	1000	1000	1001	1000
1004	1037	2001	1001	1000	1000	1000	18121	17166	2000	1000	1000	1001	1000
1004	1033	2001	1001	1000	1000	1000	18169	16814	2000	1000	1000	1001	1000
1004	1033	2001	1001	1000	1000	1000	18473	16813	2000	1000	1000	1001	1000
1004	1065	2001	1001	1000	1000	1000	17997	16814	2000	1000	1000	1001	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6], #8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0061

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	101332	70163	50107	10051	10005	40245	10045	10003	2660361	766993	794534	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100076	70104	50101	10003	10000	40104	10003	10003	2659987	766884	794422	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100067	70103	50101	10002	10000	40104	10003	10003	2660042	766932	794467	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100067	70103	50101	10002	10000	40104	10003	10003	2660042	766932	794467	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100067	70103	50101	10002	10000	40104	10003	10003	2660042	766932	794467	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100067	70103	50101	10002	10000	40104	10003	10003	2660042	766932	794467	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100067	70103	50101	10002	10000	40104	10003	10012	2661603	767333	794923	60158	30239	10012	10013	60218	10004	10003	50001	10000	40100
50204	100067	70103	50101	10002	10000	40104	10003	10003	2660042	766932	794467	60110	30209	10004	10003	60276	10013	10013	50008	10000	40100
50204	100076	70104	50101	10003	10000	40104	10003	10003	2660096	766950	794485	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100067	70103	50101	10002	10000	40104	10003	10003	2660042	766932	794467	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0074

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50030	101216	70082	50023	10053	10006	40185	10052	10003	2660105	767412	794952	60020	30029	10004	10003	60038	10004	10003	50001	10000	0	40010
50024	100066	70014	50011	10003	10000	40010	10000	10008	2661316	767721	795274	60058	30049	10009	10010	60020	10000	10000	50001	10000	0	40010
50024	100073	70013	50011	10002	10000	40010	10000	10000	2660376	767495	795012	60010	30020	10000	10000	49573	15305	6540	37566	10306	39	32005
50024	100145	70015	50011	10004	10000	40010	10000	10000	2659917	767342	794869	60010	30020	10000	10000	60098	10014	10014	50008	10000	0	40010
50024	100072	70014	50011	10003	10000	40010	10000	10000	2659890	767333	794860	60010	30020	10000	10000	60020	10000	10000	50001	10000	0	40010
50024	100059	70013	50011	10002	10000	40010	10000	10000	2659890	767333	794860	60010	30020	10000	10000	60020	10000	10000	50001	10000	0	40010
50025	100180	70026	50018	10007	10001	40045	10011	10011	2662336	768025	795586	60068	30058	10013	10013	60020	10000	10000	50001	10000	0	40010
50024	100059	70013	50011	10002	10000	40010	10000	10000	2659890	767333	794860	60010	30020	10000	10000	60020	10000	10000	50001	10000	0	40010
50024	100065	70013	50011	10002	10000	40010	10000	10000	2660106	767405	794931	60010	30020	10000	10000	60020	10000	10000	50001	10000	0	40010
50025	100134	70026	50018	10007	10001	40045	10011	10000	2659971	767360	794887	60010	30020	10000	10000	60020	10000	10000	50001	10000	0	40010

Test 3: throughput

Count: 8

Code:

  ldr d0, [x6], #8
  ldr d0, [x7], #8
  ldr d0, [x8], #8
  ldr d0, [x9], #8
  ldr d0, [x10], #8
  ldr d0, [x11], #8
  ldr d0, [x12], #8
  ldr d0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5402

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	44979	160525	80375	80150	80375	80007	240330	696577	160117	200	80014	200	80016	80009	80000	100
80204	43216	160109	80109	80000	80112	80007	240336	696414	160119	200	80016	200	80016	80009	80000	100
80204	43217	160109	80109	80000	80112	80006	240336	697096	160118	200	80016	200	80016	80009	80000	100
80204	43219	160109	80109	80000	80112	80055	240492	692908	160219	200	80072	200	80016	80009	80000	100
80204	43217	160109	80109	80000	80112	80006	240336	697060	160118	200	80016	200	80016	80009	80000	100
80204	43217	160109	80109	80000	80112	80006	240336	697060	160118	200	80016	200	80016	80009	80000	100
80204	43215	160109	80109	80000	80112	80006	240336	697060	160118	200	80016	200	80016	80009	80000	100
80204	43218	160109	80109	80000	80112	80006	240336	697132	160118	200	80016	200	80016	80009	80000	100
80204	43222	160109	80109	80000	80112	80006	240336	697150	160118	200	80016	200	80016	80009	80000	100
80204	43217	160109	80109	80000	80112	80006	240336	697096	160118	200	80016	200	80016	80009	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5402

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	44188	160429	80279	80150	80282	80011	240066	697320	160033	20	80016	20	80000	80001	80000	10
80024	43229	160011	80011	80000	80010	80000	240030	697110	160010	20	80000	20	80000	80001	80000	10
80024	43219	160011	80011	80000	80010	80000	240030	697110	160010	20	80000	20	80000	80001	80000	10
80024	43219	160011	80011	80000	80010	80000	240030	697110	160010	20	80000	20	80000	80001	80000	10
80024	43219	160011	80011	80000	80010	80000	240030	697110	160010	20	80000	20	80000	80001	80000	10
80024	43228	160011	80011	80000	80010	80000	240030	697110	160010	20	80000	20	80000	80001	80000	10
80024	43219	160011	80011	80000	80010	80058	240222	692677	160132	20	80072	20	80000	80001	80000	10
80024	43221	160011	80011	80000	80010	80000	240030	697110	160010	20	80000	20	80000	80001	80000	10
80024	43219	160011	80011	80000	80010	80000	240030	697127	160010	20	80000	20	80000	80001	80000	10
80024	43220	160011	80011	80000	80010	80000	240030	697110	160010	20	80000	20	80000	80001	80000	10

LDR (post-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations