Icestorm: LDR (post-index, Q) measurements

Code:

  ldr q0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1231	2076	1046	1030	1052	1000	17929	17154	2000	1000	1000	1001	1000
1004	1055	2001	1001	1000	1000	1000	17445	16921	2000	1000	1000	1001	1000
1004	1043	2001	1001	1000	1000	1000	17925	17658	2000	1000	1000	1001	1000
1004	1037	2001	1001	1000	1000	1000	18033	16921	2000	1000	1000	1001	1000
1004	1051	2001	1001	1000	1000	1000	17985	17315	2000	1000	1000	1001	1000
1004	1052	2001	1001	1000	1000	1000	18005	17138	2000	1000	1000	1001	1000
1004	1068	2001	1001	1000	1000	1000	17833	16938	2000	1000	1000	1001	1000
1004	1051	2001	1001	1000	1000	1000	17565	17119	2000	1000	1000	1001	1000
1004	1037	2001	1001	1000	1000	1000	18021	17316	2000	1000	1000	1001	1000
1004	1042	2001	1001	1000	1000	1000	18285	17533	2000	1000	1000	1001	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6], #8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 8.8977

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	154410	71403	50107	11291	10005	40245	10045	10003	3170600	918169	955635	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	118976	71368	50101	11267	10000	40104	10003	10003	3169898	917961	955401	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	118963	71367	50101	11266	10000	40104	10003	10003	3169898	917961	955401	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	119053	71368	50101	11267	10000	40104	10003	10003	3169898	917961	955401	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	118963	71367	50101	11266	10000	40104	10003	10003	3169520	917849	955289	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	118963	71367	50101	11266	10000	40104	10003	10003	3169898	917961	955401	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	118963	71367	50101	11266	10000	40104	10003	10012	3174312	919284	956797	60160	30239	10014	10014	60274	10013	10013	50008	10000	40100
50204	118963	71367	50101	11266	10000	40104	10003	10003	3169898	917961	955401	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	118963	71367	50101	11266	10000	40104	10003	10003	3175514	919625	957130	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	119197	71366	50101	11265	10000	40104	10003	10003	3190826	924162	962008	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 8.9003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	163122	71312	50016	11291	10005	40154	10043	10002	3170973	918703	953957	60018	30028	10003	10003	60020	10000	10000	50001	10000	40010
50024	118975	71281	50011	11270	10000	40010	10000	10000	3170994	918749	955707	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	119003	71283	50011	11272	10000	40010	10000	10000	3170616	918637	955581	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	119017	71283	50011	11272	10000	40010	10000	10000	3174261	919717	956723	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	119003	71283	50011	11272	10000	40010	10000	10000	3170994	918749	955707	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	119003	71283	50011	11272	10000	40010	10000	10000	3170994	918749	955707	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	119003	71283	50011	11272	10000	40010	10000	10000	3170994	918749	955707	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	119003	71283	50011	11272	10000	40010	10000	10000	3170994	918749	955707	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	119003	71283	50011	11272	10000	40010	10000	10000	3170994	918749	955707	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50025	119035	71293	50018	11274	10001	40045	10011	10000	3170994	918749	955707	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010

Test 3: throughput

Count: 8

Code:

  ldr q0, [x6], #8
  ldr q0, [x7], #8
  ldr q0, [x8], #8
  ldr q0, [x9], #8
  ldr q0, [x10], #8
  ldr q0, [x11], #8
  ldr q0, [x12], #8
  ldr q0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5514

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	45303	160527	80377	80150	80377	80007	240336	712091	0	160119	200	80016	0	200	80016	80009	80000	100
80204	44117	160109	80109	80000	80112	80007	240336	713130	0	160119	200	80016	0	200	80016	80009	80000	100
80204	44109	160109	80109	80000	80112	80007	240336	713202	0	160119	200	80016	0	200	80016	80009	80000	100
80204	44111	160109	80109	80000	80112	80007	240336	713202	0	160119	200	80016	0	200	80016	80009	80000	100
80204	44108	160109	80109	80000	80112	80007	240336	713094	0	160119	200	80016	0	200	80016	80009	80000	100
80204	44108	160109	80109	80000	80112	80007	240336	713202	0	160119	200	80016	0	200	80016	80009	80000	100
80204	44108	160109	80109	80000	80112	80007	240336	713130	0	160119	200	80016	0	200	80016	80009	80000	100
80204	44108	160109	80109	80000	80112	80007	240336	713166	0	160119	200	80016	0	200	80016	80009	80000	100
80204	44111	160109	80109	80000	80112	80007	240336	713094	0	160119	200	80016	0	200	80016	80009	80000	100
80204	44111	160109	80109	80000	80112	80007	240336	713202	0	160119	200	80016	0	200	80016	80009	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5516

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	45244	160429	80279	80150	80282	80011	240066	713748	160033	20	80016	20	80000	80001	80000	10
80024	44138	160011	80011	80000	80010	80000	240030	713479	160010	20	80000	20	80072	80061	80000	10
80024	44131	160011	80011	80000	80010	80000	240030	713479	160010	20	80000	20	80000	80001	80000	10
80024	44126	160011	80011	80000	80010	80000	240030	713479	160010	20	80000	20	80000	80001	80000	10
80024	44129	160011	80011	80000	80010	80000	240030	713497	160010	20	80000	20	80000	80001	80000	10
80024	44125	160011	80011	80000	80010	80000	240030	713479	160010	20	80000	20	80000	80001	80000	10
80024	44130	160011	80011	80000	80010	80000	240030	713479	160010	20	80000	20	80000	80001	80000	10
80024	44127	160011	80011	80000	80010	80000	240030	713479	160010	20	80000	20	80000	80001	80000	10
80024	44127	160011	80011	80000	80010	80000	240030	713515	160010	20	80000	20	80000	80001	80000	10
80024	44122	160011	80011	80000	80010	80000	240030	713479	160010	20	80000	20	80000	80001	80000	10

LDR (post-index, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations