Icestorm: LDR (pre-index, Q) measurements

Code:

  ldr q0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1247	2077	1047	1030	1052	1000	17797	17047	2000	1000	1000	1001	1000
1004	1046	2001	1001	1000	1000	1000	18033	16906	2000	1000	1000	1001	1000
1004	1055	2001	1001	1000	1000	1000	17729	16938	2000	1000	1000	1001	1000
1004	1047	2001	1001	1000	1000	1000	18145	17605	2000	1000	1000	1001	1000
1004	1051	2001	1001	1000	1000	1000	17121	17424	2000	1000	1000	1001	1000
1004	1051	2001	1001	1000	1000	1000	17977	16957	2000	1000	1000	1001	1000
1004	1040	2001	1001	1000	1000	1000	18357	16942	2000	1000	1000	1001	1000
1004	1041	2001	1001	1000	1000	1000	18325	16959	2000	1000	1000	1001	1000
1004	1071	2001	1001	1000	1000	1000	17965	16810	2000	1000	1000	1001	1000
1004	1043	2001	1001	1000	1000	1000	18553	16959	2000	1000	1000	1001	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, #8]!
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 8.9003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	153495	71403	50107	11291	10005	40245	10046	10002	3171255	909318	955796	60108	30208	10003	10003	60218	10004	10003	50001	10000	40100
50205	119210	71381	50106	11274	10001	40135	10013	10003	3171345	908518	955005	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	119003	71373	50101	11272	10000	40104	10003	10003	3170994	908427	954901	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	119003	71373	50101	11272	10000	40104	10003	10003	3170994	908427	954901	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	119003	71373	50101	11272	10000	40104	10003	10003	3170994	908427	954901	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	119003	71373	50101	11272	10000	40104	10003	10003	3170994	908427	954901	60110	30209	10004	10003	60278	10013	10013	50008	10000	40100
50204	119003	71373	50101	11272	10000	40104	10003	10003	3170994	908427	954901	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	119003	71373	50101	11272	10000	40104	10003	10003	3170994	908427	954901	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	119387	71373	50101	11272	10000	40104	10003	10003	3173181	909046	955601	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	119003	71373	50101	11272	10000	40104	10003	10003	3170994	908427	954901	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 8.8964

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	182774	71310	50016	11289	10005	40154	10043	10003	3170971	909356	955852	60020	30029	10004	10003	60020	10000	10000	50001	10000	40010
50025	119247	71294	50018	11275	10001	40045	10011	10000	3170356	909185	955648	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	118964	71280	50011	11269	10000	40010	10000	10000	3170005	909081	955531	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	118964	71280	50011	11269	10000	40010	10000	10000	3170005	909081	955531	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	118964	71280	50011	11269	10000	40010	10000	10000	3170005	909081	955531	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	118964	71280	50011	11269	10000	40010	10000	10000	3170005	909081	955531	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	118964	71280	50011	11269	10000	40010	10000	10000	3170005	909081	955531	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	118964	71280	50011	11269	10000	40010	10000	10000	3170005	909081	955531	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	118964	71280	50011	11269	10000	40010	10000	10000	3169627	908969	955405	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010
50024	118964	71280	50011	11269	10000	40010	10000	10000	3170005	909081	955531	60010	30020	10000	10000	60020	10000	10000	50001	10000	40010

Test 3: throughput

Count: 8

Code:

  ldr q0, [x6, #8]!
  ldr q0, [x7, #8]!
  ldr q0, [x8, #8]!
  ldr q0, [x9, #8]!
  ldr q0, [x10, #8]!
  ldr q0, [x11, #8]!
  ldr q0, [x12, #8]!
  ldr q0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5514

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	45317	160521	80371	80150	80374	80007	240324	712810	160115	200	80012	200	80012	80005	80000	100
80204	44116	160105	80105	80000	80108	80007	240324	713204	160115	200	80012	200	80012	80005	80000	100
80204	44110	160105	80105	80000	80108	80007	240324	713168	160115	200	80012	200	80066	80058	80000	100
80204	44108	160105	80105	80000	80108	80007	240324	713402	160115	200	80012	200	80012	80005	80000	100
80204	44110	160105	80105	80000	80108	80007	240324	713204	160115	200	80012	200	80012	80005	80000	100
80204	44110	160105	80105	80000	80108	80007	240324	713204	160115	200	80012	200	80012	80005	80000	100
80204	44110	160105	80105	80000	80108	80007	240324	713168	160115	200	80012	200	80012	80005	80000	100
80204	44110	160105	80105	80000	80108	80007	240324	713168	160115	200	80012	200	80012	80005	80000	100
80204	44122	160105	80105	80000	80108	80007	240324	713204	160115	200	80012	200	80012	80005	80000	100
80204	44125	160105	80105	80000	80108	80007	240324	713240	160115	200	80012	200	80012	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5517

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	45473	160431	80281	80150	80280	80007	240054	713728	160025	20	80012	20	80000	80001	80000	10
80024	44136	160011	80011	80000	80010	80000	240030	713715	160010	20	80000	20	80000	80001	80000	10
80024	44138	160011	80011	80000	80010	80000	240030	713715	160010	20	80000	20	80000	80001	80000	10
80024	44138	160011	80011	80000	80010	80000	240030	713715	160010	20	80000	20	80000	80001	80000	10
80024	44138	160011	80011	80000	80010	80000	240030	713715	160010	20	80000	20	80000	80001	80000	10
80024	44138	160011	80011	80000	80010	80000	240030	713715	160010	20	80000	20	80000	80001	80000	10
80024	44138	160011	80011	80000	80010	80000	240030	713715	160010	20	80000	20	80000	80001	80000	10
80024	44138	160011	80011	80000	80010	80000	240030	713715	160010	20	80000	20	80000	80001	80000	10
80024	44138	160011	80011	80000	80010	80000	240030	713715	160010	20	80000	20	80000	80001	80000	10
80024	44138	160011	80011	80000	80010	80000	240030	713715	160010	20	80000	20	80000	80001	80000	10

LDR (pre-index, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations