Icestorm: LDR (pre-index, S) measurements

Code:

  ldr s0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1246	2076	1046	1030	1052	1000	18053	16904	2000	1000	1000	1001	1000
1004	1045	2001	1001	1000	1000	1000	18317	17032	2000	1000	1000	1001	1000
1004	1081	2001	1001	1000	1000	1000	18113	17519	2000	1000	1000	1001	1000
1004	1051	2001	1001	1000	1000	1000	18493	16997	2000	1000	1000	1001	1000
1004	1046	2001	1001	1000	1000	1000	18429	16974	2000	1000	1000	1001	1000
1004	1041	2001	1001	1000	1000	1000	17733	17645	2000	1000	1000	1001	1000
1004	1062	2001	1001	1000	1000	1000	17321	17087	2000	1000	1000	1001	1000
1004	1066	2001	1001	1000	1000	1000	17869	17622	2000	1000	1000	1001	1000
1004	1043	2001	1001	1000	1000	1000	18153	17030	2000	1000	1000	1001	1000
1004	1085	2001	1001	1000	1000	1000	18765	17106	2000	1000	1000	1001	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, #8]!
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0106

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	101117	70161	50107	10049	10005	40245	10045	10011	2661930	767466	795006	60158	30238	10013	10013	60218	10004	10003	50001	10000	40100
50204	100066	70104	50101	10003	10000	40104	10003	10003	2659826	766878	794410	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100059	70103	50101	10002	10000	40104	10003	10003	2659826	766878	794410	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100059	70103	50101	10002	10000	40104	10003	10003	2659826	766878	794410	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100059	70103	50101	10002	10000	40104	10003	10003	2659826	766878	794410	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100059	70103	50101	10002	10000	40104	10003	10003	2659826	766878	794410	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50205	100128	70118	50110	10007	10001	40137	10013	10003	2659826	766878	794410	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100059	70103	50101	10002	10000	40104	10003	10003	2659826	766878	794410	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100059	70103	50101	10002	10000	40104	10003	10003	2659826	766878	794410	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100
50204	100059	70103	50101	10002	10000	40104	10003	10003	2659826	766878	794410	60110	30209	10004	10003	60218	10004	10003	50001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0086

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50029	101415	70068	50016	10047	10005	40154	10043	10003	2659943	767382	794914	60020	30029	10004	10003	60020	10000	10000	50001	10000	0	40010
50024	100075	70013	50011	10002	10000	40010	10000	10038	2666419	769331	796898	60228	30139	10038	10040	60080	10010	10011	50008	10000	0	40010
50024	100060	70013	50011	10002	10000	40010	10000	10000	2659890	767343	794869	60010	30020	10000	10000	60020	10000	10000	50001	10000	0	40010
50024	100084	70013	50011	10002	10000	40010	10000	10000	2660268	767463	794989	60010	30020	10000	10000	60020	10000	10000	50001	10000	0	40010
50024	100059	70013	50011	10002	10000	40010	10000	10000	2659890	767343	794869	60010	30020	10000	10000	60020	10000	10000	50001	10000	0	40010
50024	100425	70073	50051	10014	10008	40150	10041	10000	2660025	767386	794912	60010	30020	10000	10000	60020	10000	10000	50001	10000	0	40010
50024	100059	70013	50011	10002	10000	40010	10000	10000	2659890	767343	794869	60010	30020	10000	10000	60020	10000	10000	50001	10000	0	40010
50024	100471	70074	50052	10013	10009	40147	10040	10000	2659917	767352	794878	60010	30020	10000	10000	60098	10014	10014	50008	10000	0	40010
50024	100060	70013	50011	10002	10000	40010	10000	10000	2659890	767343	794869	60010	30020	10000	10000	60020	10000	10000	50001	10000	0	40010
50024	100060	70013	50011	10002	10000	40010	10000	10000	2660457	767522	795048	60010	30020	10000	10000	60098	10012	10013	50008	10000	0	40010

Test 3: throughput

Count: 8

Code:

  ldr s0, [x6, #8]!
  ldr s0, [x7, #8]!
  ldr s0, [x8, #8]!
  ldr s0, [x9, #8]!
  ldr s0, [x10, #8]!
  ldr s0, [x11, #8]!
  ldr s0, [x12, #8]!
  ldr s0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5404

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	44485	160522	80372	80150	80374	80007	240324	696818	160115	200	80012	200	80012	80009	80000	100
80204	43599	160106	80106	80000	80109	80007	240324	696516	160115	200	80012	200	80012	80005	80000	100
80204	43229	160105	80105	80000	80108	80006	240324	697280	160114	200	80012	200	80012	80005	80000	100
80204	43224	160105	80105	80000	80108	80006	240324	697280	160114	200	80012	200	80012	80005	80000	100
80204	43224	160105	80105	80000	80108	80006	240324	697280	160114	200	80012	200	80012	80005	80000	100
80204	43224	160105	80105	80000	80108	80006	240324	697280	160114	200	80012	200	80012	80005	80000	100
80204	43224	160105	80105	80000	80108	80006	240324	697280	160114	200	80012	200	80012	80005	80000	100
80204	43224	160105	80105	80000	80108	80006	240324	697280	160114	200	80012	200	80012	80005	80000	100
80204	43224	160105	80105	80000	80108	80006	240324	697280	160114	200	80012	200	80012	80005	80000	100
80204	43224	160105	80105	80000	80108	80006	240324	697280	160114	200	80012	200	80012	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5402

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	44686	160429	80279	80150	80278	80007	240054	697474	160025	20	80012	20	80000	80001	80000	10
80024	43222	160011	80011	80000	80010	80000	240030	697126	160010	20	80000	20	80000	80001	80000	10
80024	43230	160011	80011	80000	80010	80000	240030	697432	160010	20	80000	20	80000	80001	80000	10
80024	43219	160011	80011	80000	80010	80000	240030	697126	160010	20	80000	20	80000	80001	80000	10
80024	43219	160011	80011	80000	80010	80000	240030	697277	160010	20	80000	20	80000	80001	80000	10
80024	43218	160011	80011	80000	80010	80000	240030	697126	160010	20	80000	20	80000	80001	80000	10
80024	43219	160011	80011	80000	80010	80000	240030	682547	160010	20	80000	20	80000	80001	80000	10
80024	43219	160011	80011	80000	80010	80000	240030	697126	160010	20	80000	20	80000	80001	80000	10
80024	43220	160011	80011	80000	80010	80000	240030	697468	160010	20	80000	20	80000	80001	80000	10
80024	43228	160011	80011	80000	80010	80000	240030	697115	160010	20	80000	20	80000	80001	80000	10

LDR (pre-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations