Icestorm: LDR (register, D) measurements

Code:

  ldr d0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	645	1031	1	1030	1000	8164	1000	1000	2000	1	1000
1004	553	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, x7]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100147	60108	40101	10006	10001	30130	10014	10003	2669129	1045473	1070654	50109	30210	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100040	60102	40101	10001	10000	30103	10003	10015	2669517	1045729	1070955	50163	30250	10016	10017	60224	20008	10004	40001	10000	40100
50204	100050	60102	40101	10001	10000	30103	10003	10016	2669525	1045730	1070902	50164	30251	10016	10017	60224	20008	10004	40001	10000	40100
50204	100043	60102	40101	10001	10000	30103	10003	10003	2669005	1045479	1070654	50109	30210	10004	10004	60296	20036	10016	40005	10000	40100
50204	100066	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100155	60018	40011	10006	10001	30040	10015	10004	2669356	1046989	1072029	50020	30032	10004	10004	60040	20008	10004	40001	10000	40010
50024	100049	60013	40011	10002	10000	30013	10003	10004	2669167	1046912	1071952	50020	30032	10004	10004	60044	20008	10004	40001	10000	40010
50024	100042	60012	40011	10001	10000	30013	10003	10004	2669194	1046924	1071963	50020	30032	10004	10004	60044	20008	10004	40001	10000	40010
50024	100042	60012	40011	10001	10000	30013	10003	10004	2669167	1046912	1071952	50020	30032	10004	10004	60044	20008	10004	40001	10000	40010
50024	100042	60012	40011	10001	10000	30013	10003	10004	2669167	1046912	1071952	50020	30032	10004	10004	60044	20008	10004	40001	10000	40010
50024	100046	60012	40011	10001	10000	30013	10003	10004	2669194	1046924	1071963	50020	30032	10004	10004	60044	20008	10004	40001	10000	40010
50024	100045	60012	40011	10001	10000	30013	10003	10004	2669221	1046934	1071974	50020	30032	10004	10004	60044	20008	10004	40001	10000	40010
50024	100042	60012	40011	10001	10000	30013	10003	10004	2669167	1046912	1071952	50020	30032	10004	10004	60044	20008	10004	40001	10000	40010
50024	100052	60012	40011	10001	10000	30013	10003	10004	2669464	1047039	1072077	50020	30032	10004	10004	60044	20008	10004	40001	10000	40010
50024	100042	60012	40011	10001	10000	30013	10003	10004	2669167	1046912	1071952	50020	30032	10004	10004	60044	20008	10004	40001	10000	40010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, x7]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100221	60108	40101	10006	10001	30130	10015	10003	2669880	1045779	1070963	50109	30210	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60220	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50205	100077	60111	40105	10004	10002	30133	10015	10004	2669401	1045698	1070872	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100155	60018	40011	10006	10001	30040	10015	10000	2669238	1046842	1071887	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2670983	1047646	1072660	50010	30020	10000	10000	60114	20034	10016	40005	10000	40010
50024	100051	60013	40011	10002	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010

Test 4: throughput

Count: 8

Code:

  ldr d0, [x6, x7]
  ldr d0, [x6, x7]
  ldr d0, [x6, x7]
  ldr d0, [x6, x7]
  ldr d0, [x6, x7]
  ldr d0, [x6, x7]
  ldr d0, [x6, x7]
  ldr d0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40168	80131	101	80030	100	80008	300	280188	80108	200	80012	200	160142	1	80000	100
80204	40059	80101	101	80000	100	80059	300	642204	80159	200	80071	200	160028	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40061	80101	101	80000	100	80008	300	640356	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80059	300	646042	80159	200	80072	200	160024	1	80000	100
82282	53460	82282	1415	80867	1471	80008	300	640248	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40318	80045	11	80034	10	80010	30	640260	80020	20	80014	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40122	80011	11	80000	10	80000	30	640326	80010	20	80000	20	160000	1	80000	10
80024	40066	80011	11	80000	10	80000	30	640308	80010	20	80000	20	160000	1	80000	10

LDR (register, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations