Icestorm: LDR (register, Q) measurements

Code:

  ldr q0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1076	1031	1	1030	1000	8164	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, x7]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0048

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50205	100151	60108	40101	10006	10001	30130	10015	10003	2669183	1045495	1070676	50109	30210	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	64820	23937	10404	42057	11956	136	42784
50205	100079	60112	40107	10004	10001	30133	10015	10003	2669167	1045545	1070720	50109	30210	10004	10004	60224	20008	10004	40001	10000	0	40100
50205	100109	60113	40107	10005	10001	30133	10015	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100050	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100157	60018	40011	10006	10001	30040	10015	10003	2669258	1046894	1071935	50019	30030	10004	10004	60040	20008	10004	40001	10000	40010
50024	100047	60013	40011	10002	10000	30013	10003	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2670497	1047422	1072454	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669471	1046995	1072027	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100048	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	101282	60170	40107	10037	10026	30403	10158	10004	2669302	1046967	1072007	50020	30032	10004	10004	60044	20008	10004	40001	10000	40010
50024	100076	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, x7]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50205	100153	60108	40101	10006	10001	30130	10015	10003	2669178	1045492	1070672	50109	30210	10004	10004	60220	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100030	60101	40101	10000	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50205	100084	60111	40107	10003	10001	30133	10015	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100044	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100293	60018	40011	10006	10001	30040	10015	10003	2669312	1046916	1071957	50019	30030	10004	10004	60040	20008	10004	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100056	60012	40011	10001	10000	30010	10000	10000	2669228	1046894	1071931	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2670902	1047605	1072624	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010

Test 4: throughput

Count: 8

Code:

  ldr q0, [x6, x7]
  ldr q0, [x6, x7]
  ldr q0, [x6, x7]
  ldr q0, [x6, x7]
  ldr q0, [x6, x7]
  ldr q0, [x6, x7]
  ldr q0, [x6, x7]
  ldr q0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40164	80137	101	80036	100	80008	300	256242	80108	200	80012	200	160028	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80205	40110	80138	101	80037	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40273	80047	11	80036	10	80057	30	618084	80067	20	80069	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40075	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40196	80017	11	80006	10	80000	30	400164	80010	20	80000	20	160000	1	80000	10
80024	40057	80011	11	80000	10	80000	30	640218	80010	20	80000	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	160000	1	80000	10

LDR (register, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations