Icestorm: LDR (register, S) measurements

Code:

  ldr s0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	667	1031	1	1030	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, x7]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100152	60108	40101	10006	10001	30130	10015	10003	2669178	1045492	1070672	50109	30210	10004	10004	60220	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60294	20032	10017	40007	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10017	2669380	1045615	1070819	50165	30248	10017	10016	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669158	1045596	1070770	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100040	60102	40101	10001	10000	30103	10003	10003	2668933	1045390	1070573	50109	30210	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100157	60018	40011	10006	10001	30040	10015	10003	2669312	1046916	1071957	50019	30030	10004	10004	60020	20000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100051	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50025	100081	60022	40017	10004	10001	30043	10015	10000	2669633	1047062	1072095	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669444	1046983	1072016	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100052	60013	40011	10002	10000	30013	10003	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, x7]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100310	60108	40101	10006	10001	30130	10015	10003	2669221	1045567	1070742	50109	30210	10004	10004	60224	20008	10004	40001	10000	40100
50204	100051	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60220	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10014	2669613	1045768	1070967	50162	30248	10016	10017	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50205	100126	60111	40107	10003	10001	30133	10015	10004	2669293	1045652	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50025	100156	60018	40011	10006	10001	30040	10015	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50025	100072	60020	40015	10003	10002	30043	10015	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100045	60012	40011	10001	10000	30010	10000	10000	2669201	1046880	1071917	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010

Test 4: throughput

Count: 8

Code:

  ldr s0, [x6, x7]
  ldr s0, [x6, x7]
  ldr s0, [x6, x7]
  ldr s0, [x6, x7]
  ldr s0, [x6, x7]
  ldr s0, [x6, x7]
  ldr s0, [x6, x7]
  ldr s0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40217	80137	101	80036	100	80008	300	256242	80108	200	80012	200	160024	1	80000	100
80204	40048	80101	101	80000	100	80008	300	640028	80108	200	80012	200	160028	1	80000	100
80204	40059	80101	101	80000	100	80008	300	280006	80108	200	80012	200	160024	1	80000	100
80204	40051	80105	101	80004	100	80008	300	640012	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640012	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640120	80108	200	80012	200	160024	1	80000	100
80204	40050	80101	101	80000	100	80008	300	640012	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640120	80108	200	80012	200	160024	1	80000	100
80204	40048	80101	101	80000	100	80008	300	640066	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640012	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40319	80045	11	80034	10	80008	30	400022	80018	20	80012	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640322	80010	20	80000	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640160	80010	20	80000	20	160000	1	80000	10
80025	40101	80048	11	80037	10	80000	30	240000	80010	20	80000	20	160000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	10

LDR (register, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations