Icestorm: LDR (register, lsl, D) measurements

Code:

  ldr d0, [x6, x7, lsl #3]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	678	1031	1	1030	1000	7986	1000	1000	2000	1	1000
1004	544	1001	1	1000	1000	7986	1000	1000	2000	1	1000
1004	544	1001	1	1000	1000	7986	1000	1000	2000	1	1000
1004	544	1001	1	1000	1000	7986	1000	1000	2000	1	1000
1004	544	1001	1	1000	1000	8076	1000	1000	2000	1	1000
1004	544	1001	1	1000	1000	7986	1000	1000	2000	1	1000
1004	544	1001	1	1000	1000	7986	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	7986	1000	1000	2000	1	1000
1004	544	1001	1	1000	1000	7986	1000	1000	2000	1	1000
1004	544	1001	1	1000	1000	7986	1000	1000	2000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, x7, lsl #3]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0048

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100147	60108	40101	10006	10001	30130	10015	10003	2669151	1045481	1070661	50109	30210	10004	10004	60220	20008	10004	40001	10000	40100
50204	100048	60103	40101	10002	10000	30103	10003	10004	2669239	1045629	1070803	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100048	60103	40101	10002	10000	30103	10003	10004	2669239	1045629	1070803	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100048	60103	40101	10002	10000	30103	10003	10004	2669239	1045629	1070803	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100059	60103	40101	10002	10000	30103	10003	10004	2669320	1045662	1070836	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100048	60103	40101	10002	10000	30103	10003	10004	2669239	1045629	1070803	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100048	60103	40101	10002	10000	30103	10003	10004	2669239	1045629	1070803	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100048	60103	40101	10002	10000	30103	10003	10016	2669550	1045740	1071020	50164	30250	10017	10017	60224	20008	10004	40001	10000	40100
50204	100048	60103	40101	10002	10000	30103	10003	10004	2669239	1045629	1070803	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100048	60103	40101	10002	10000	30103	10003	10004	2669239	1045629	1070803	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0041

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100156	60018	40011	10006	10001	30040	10015	10000	2669265	1046853	1071898	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100048	60013	40011	10002	10000	30010	10000	10000	2669309	1046924	1071961	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100048	60013	40011	10002	10000	30010	10000	10000	2669309	1046924	1071961	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100048	60013	40011	10002	10000	30010	10000	10000	2669309	1046924	1071961	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100048	60013	40011	10002	10000	30010	10000	10000	2669309	1046924	1071961	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100048	60013	40011	10002	10000	30010	10000	10000	2669309	1046924	1071961	50010	30020	10000	10000	60122	20032	10017	40007	10000	40010
50024	100053	60012	40011	10001	10000	30010	10000	10000	2669120	1046847	1071884	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100041	60012	40011	10001	10000	30010	10000	10000	2669417	1046968	1072005	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100041	60012	40011	10001	10000	30010	10000	10000	2669120	1046847	1071884	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100041	60012	40011	10001	10000	30010	10000	10016	2670933	1047645	1072690	50074	30067	10017	10016	60020	20000	10000	40001	10000	40010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, x7, lsl #3]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0048

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50205	100156	60108	40101	10006	10001	30130	10015	10003	2669232	1045460	1070647	50109	30210	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100053	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100052	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100050	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100050	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60294	20034	10016	40005	10000	0	40100
50204	100050	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100050	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100050	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100050	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100050	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60300	20034	10017	40007	10000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0041

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100220	60018	40011	10006	10001	30040	10015	10003	2669474	1046983	1072024	50019	30030	10004	10004	60020	20000	10000	40001	10000	40010
50024	100048	60013	40011	10002	10000	30010	10000	10000	2669120	1046847	1071884	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100041	60012	40011	10001	10000	30010	10000	10026	2672102	1048094	1073134	50127	30107	10029	10030	60020	20000	10000	40001	10000	40010
50024	100041	60012	40011	10001	10000	30010	10000	10000	2669120	1046847	1071884	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100041	60012	40011	10001	10000	30010	10000	10000	2669120	1046847	1071884	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100041	60012	40011	10001	10000	30010	10000	10000	2669120	1046847	1071884	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100041	60012	40011	10001	10000	30010	10000	10000	2669120	1046847	1071884	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100041	60012	40011	10001	10000	30010	10000	10000	2669120	1046847	1071884	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100041	60012	40011	10001	10000	30010	10000	10000	2669120	1046847	1071884	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100041	60012	40011	10001	10000	30010	10000	10000	2669120	1046847	1071884	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010

Test 4: throughput

Count: 8

Code:

  ldr d0, [x6, x7, lsl #3]
  ldr d0, [x6, x7, lsl #3]
  ldr d0, [x6, x7, lsl #3]
  ldr d0, [x6, x7, lsl #3]
  ldr d0, [x6, x7, lsl #3]
  ldr d0, [x6, x7, lsl #3]
  ldr d0, [x6, x7, lsl #3]
  ldr d0, [x6, x7, lsl #3]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80204	40075	80105	101	80004	100	80008	300	472242	80108	200	80012	200	160028	1	80000	100
80204	40057	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160028	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40268	80045	11	80034	10	80008	30	440490	0	80018	20	80012	0	20	160028	1	80000	10
80024	40124	80011	11	80000	10	80010	30	641394	0	80020	20	80014	0	20	160000	1	80000	10
80024	40113	80011	11	80000	10	80000	30	641262	0	80010	20	80000	0	20	160000	1	80000	10
80024	40379	80015	11	80004	10	80000	30	575186	0	80010	20	80000	0	20	160000	1	80000	10
80024	40062	80011	11	80000	10	80000	30	640164	0	80010	20	80000	0	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	0	80010	20	80000	0	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	0	80010	20	80000	0	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	641226	0	80010	20	80000	0	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640272	0	80010	20	80000	0	20	160000	1	80000	10
80024	40121	80011	11	80000	10	80000	30	640164	0	80010	20	80000	0	20	160000	1	80000	10

LDR (register, lsl, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations