Icestorm: LDR (register, lsl, Q) measurements

Code:

  ldr q0, [x6, x7, lsl #4]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2006	704	2063	1033	1030	1032	1000	3000	4180	2000	1000	1000	1000	2000	1001	1000	1000
2004	555	2001	1001	1000	1000	1000	3000	4180	2000	1000	1000	1000	2000	1001	1000	1000
2004	555	2001	1001	1000	1000	1000	3000	4180	2000	1000	1000	1000	2000	1001	1000	1000
2004	555	2001	1001	1000	1000	1000	3000	4180	2000	1000	1000	1000	2000	1001	1000	1000
2004	555	2001	1001	1000	1000	1000	3000	4180	2000	1000	1000	1000	2000	1001	1000	1000
2004	555	2001	1001	1000	1000	1000	3000	4180	2000	1000	1000	1000	2000	1001	1000	1000
2004	555	2001	1001	1000	1000	1000	3000	4180	2000	1000	1000	1000	2000	1001	1000	1000
2004	555	2001	1001	1000	1000	1000	3000	4180	2000	1000	1000	1000	2000	1001	1000	1000
2004	555	2001	1001	1000	1000	1000	3000	4180	2000	1000	1000	1000	2000	1001	1000	1000
2004	555	2001	1001	1000	1000	1000	3000	4180	2000	1000	1000	1000	2000	1001	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, x7, lsl #4]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0043

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60207	100196	70137	50126	10009	10002	40179	10023	10003	2659195	978637	983895	60109	40212	10003	10003	70221	20006	10003	50002	10000	50100
60204	100048	70104	50102	10002	10000	40104	10002	10003	2659043	978621	983868	60110	40210	10003	10003	70217	20006	10003	50002	10000	50100
60204	100041	70103	50102	10001	10000	40104	10003	10003	2659043	978621	983868	60110	40210	10003	10003	70217	20006	10003	50002	10000	50100
60204	100041	70103	50102	10001	10000	40104	10003	10003	2658770	978521	983760	60110	40210	10003	10003	70217	20006	10003	50002	10000	50100
60204	100041	70103	50102	10001	10000	40104	10003	10003	2659043	978621	983868	60110	40210	10003	10003	70217	20006	10003	50002	10000	50100
60204	100041	70103	50102	10001	10000	40104	10003	10003	2659043	978621	983868	60110	40210	10003	10003	70293	20026	10014	50017	10000	50100
60204	100041	70103	50102	10001	10000	40104	10003	10003	2659043	978621	983868	60110	40210	10003	10003	70217	20006	10003	50002	10000	50100
60204	100041	70103	50102	10001	10000	40104	10003	10003	2659043	978621	983868	60110	40210	10003	10003	70217	20006	10003	50002	10000	50100
60204	100041	70103	50102	10001	10000	40104	10003	10003	2659124	978654	983901	60110	40210	10003	10003	70217	20006	10003	50002	10000	50100
60204	100041	70103	50102	10001	10000	40104	10003	10003	2659043	978621	983868	60110	40210	10003	10003	70217	20006	10003	50002	10000	50100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0043

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60026	100171	70029	50021	10007	10001	40050	10013	10000	2660926	980176	985237	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	100052	70013	50011	10002	10000	40010	10000	10000	2659117	979448	984517	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	100041	70012	50011	10001	10000	40010	10000	10000	2659117	979448	984517	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	100041	70012	50011	10001	10000	40010	10000	10000	2659117	979448	984517	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	100041	70012	50011	10001	10000	40010	10000	10000	2659117	979448	984517	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	100041	70012	50011	10001	10000	40010	10000	10000	2659117	979448	984517	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	100041	70012	50011	10001	10000	40010	10000	10000	2659117	979448	984517	60010	40020	10000	10000	70107	20026	10013	50017	10000	50010
60024	100045	70012	50011	10001	10000	40010	10000	10013	2659490	979585	984656	60080	40073	10013	10014	70020	20000	10000	50001	10000	50010
60024	100046	70012	50011	10001	10000	40010	10000	10000	2659117	979448	984517	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	100041	70012	50011	10001	10000	40010	10000	10000	2659117	979448	984517	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, x7, lsl #4]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 8.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60206	110164	70110	50102	10007	10001	40132	10012	10003	2929301	873644	873758	60109	40212	10003	10003	70222	20008	10003	50001	10000	50100
60204	110047	70103	50101	10002	10000	40104	10003	10012	2929779	873858	873962	60160	40253	10014	10013	70292	20028	10013	50007	10000	50100
60204	110060	70103	50101	10002	10000	40104	10002	10012	2931669	874482	874567	60160	40253	10014	10013	70222	20008	10003	50001	10000	50100
60204	110047	70103	50101	10002	10000	40104	10003	10003	2929394	873753	873852	60110	40213	10004	10003	70222	20008	10003	50001	10000	50100
60204	110047	70103	50101	10002	10000	40104	10003	10003	2929394	873753	873852	60110	40213	10004	10003	70222	20008	10003	50001	10000	50100
60204	110049	70103	50101	10002	10000	40104	10003	10003	2931014	874292	874359	60110	40213	10004	10003	70290	20024	10013	50008	10000	50100
60204	110051	70103	50101	10002	10000	40104	10003	10003	2929355	873660	873776	60109	40212	10003	10003	70222	20008	10003	50001	10000	50100
60204	110049	70103	50101	10002	10000	40104	10003	10003	2929448	873769	873870	60110	40213	10004	10003	70222	20008	10003	50001	10000	50100
60204	110049	70103	50101	10002	10000	40104	10003	10003	2929448	873769	873870	60110	40213	10004	10003	70222	20008	10003	50001	10000	50100
60204	110049	70103	50101	10002	10000	40104	10003	10003	2929448	873769	873870	60110	40213	10004	10003	70222	20008	10003	50001	10000	50100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 8.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60026	110169	70020	50012	10007	10001	40042	10012	10000	2929273	874580	874631	60010	40020	10000	10000	70112	20028	10013	50007	10000	50010
60024	110040	70012	50011	10001	10000	40010	10000	10000	2929273	874580	874631	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	110103	70012	50011	10001	10000	40010	10000	10000	2929732	874729	874778	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	110040	70012	50011	10001	10000	40010	10000	10000	2929273	874580	874631	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	110040	70012	50011	10001	10000	40010	10000	10000	2929273	874580	874631	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	110040	70012	50011	10001	10000	40010	10000	10000	2929273	874580	874631	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60025	110072	70021	50017	10003	10001	40041	10010	10000	2929273	874580	874631	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	110040	70012	50011	10001	10000	40010	10000	10000	2929273	874580	874631	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	110040	70012	50011	10001	10000	40010	10000	10000	2929273	874580	874631	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010
60024	110040	70012	50011	10001	10000	40010	10000	10000	2929273	874580	874631	60010	40020	10000	10000	70020	20000	10000	50001	10000	50010

Test 4: throughput

Count: 8

Code:

  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]
  ldr q0, [x6, x7, lsl #4]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5014

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160204	40433	160117	80109	80008	80112	80012	240336	326036	160124	80212	80012	80212	160024	80009	80000	80100
160204	40129	160117	80109	80008	80112	80012	240336	326918	160124	80212	80012	80212	160024	80009	80000	80100
160204	40117	160117	80109	80008	80112	80012	240336	324284	160124	80212	80012	80212	160024	80009	80000	80100
160204	40116	160117	80109	80008	80112	80012	240336	320206	160124	80212	80012	80212	160024	80009	80000	80100
160204	40116	160117	80109	80008	80112	80012	240336	323264	160124	80212	80012	80212	160024	80009	80000	80100
160204	40119	160117	80109	80008	80112	80012	240336	320206	160124	80212	80012	80212	160024	80009	80000	80100
160204	40116	160117	80109	80008	80112	80012	240336	320206	160124	80212	80012	80212	160024	80009	80000	80100
160204	40116	160117	80109	80008	80112	80012	240336	320206	160124	80212	80012	80212	160024	80009	80000	80100
160204	40116	160117	80109	80008	80112	80012	240336	320206	160124	80212	80012	80212	160024	80009	80000	80100
160204	40116	160117	80109	80008	80112	80012	240336	320206	160124	80212	80012	80212	160024	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160026	40651	160089	80051	80038	80054	80012	240066	320206	160034	80032	80012	80020	160000	0	80001	80000	0	80010
160024	40077	160011	80011	80000	80010	80042	240156	320326	160094	80062	80042	80020	160000	0	80001	80000	0	80010
160024	40064	160011	80011	80000	80010	80000	240030	320162	160010	80020	80000	80020	160000	0	80001	80000	0	80010
160024	40064	160011	80011	80000	80010	80000	240030	320162	160010	80020	80000	80020	160000	0	80001	80000	0	80010
160024	40064	160011	80011	80000	80010	80000	240030	320162	160010	80020	80000	80020	160000	0	80001	80000	0	80010
160024	40064	160011	80011	80000	80010	80000	240030	320162	160010	80020	80000	80020	160000	0	80001	80000	0	80010
160024	40064	160011	80011	80000	80010	80000	240030	320162	160010	80020	80000	80020	160000	0	80001	80000	0	80010
160024	40075	160011	80011	80000	80010	80000	240030	369452	160010	80020	80000	80020	160000	0	80001	80000	0	80010
160024	41092	160011	80011	80000	80010	80000	240030	320162	160010	80020	80000	80020	160000	0	80001	80000	0	80010
160024	40066	160011	80011	80000	80010	80000	240030	320162	160010	80020	80000	80020	160000	0	80001	80000	0	80010

LDR (register, lsl, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations