Icestorm: LDR (register, lsl, S) measurements

Code:

  ldr s0, [x6, x7, lsl #2]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	792	1031	1	1030	1000	8128	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8066	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, x7, lsl #2]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100160	60108	40101	10006	10001	30130	10015	10003	2669221	1045567	1070742	50109	30210	10004	10004	60224	20008	10004	40001	10000	40100
50204	100069	60103	40101	10002	10000	30103	10003	10003	2669905	1045821	1071039	50109	30210	10004	10004	60220	20008	10004	40001	10000	40100
50204	100051	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10015	2669873	1045859	1071041	50164	30250	10017	10017	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50205	100147	60112	40107	10004	10001	30133	10015	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100155	60018	40011	10006	10001	30040	10015	10003	2669258	1046894	1071935	50019	30030	10004	10004	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2670929	1047622	1072640	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669309	1046924	1071961	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2670146	1047284	1072308	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669390	1046957	1071994	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
58614	134758	67834	44945	10008	12881	34848	10015	10000	2669616	1047004	1072045	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10011	2671944	1048016	1073056	50063	30058	10012	10013	60020	20000	10000	40001	10000	40010
50024	100048	60013	40011	10002	10000	30010	10000	10003	2669312	1046877	1071941	50019	30030	10004	10004	60020	20000	10000	40001	10000	40010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, x7, lsl #2]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50205	100152	60108	40101	10006	10001	30130	10015	10003	2669183	1045495	1070676	50109	30210	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10003	2669086	1045512	1070687	50109	30210	10004	10004	60302	20032	10017	40007	10000	0	40100
50204	100047	60103	40101	10002	10000	30103	10003	10003	2668933	1045390	1070573	50109	30210	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50205	100145	60111	40107	10003	10001	30133	10015	10004	2669050	1045552	1070726	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2671939	1046767	1071918	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100148	60018	40011	10006	10001	30040	10015	10000	2669238	1046842	1071887	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669336	1046937	1071972	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10012	2669649	1047044	1072082	50064	30059	10012	10013	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100050	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010

Test 4: throughput

Count: 8

Code:

  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40192	80137	101	80036	100	80008	300	248206	80108	200	80012	200	160024	1	80000	100
80204	40061	80105	101	80004	100	80008	300	640212	80108	200	80012	200	160024	1	80000	100
80204	40080	80101	101	80000	100	80008	300	640626	80108	200	80012	200	160144	1	80000	100
80204	40110	80101	101	80000	100	80008	300	640212	80108	200	80012	200	160024	1	80000	100
80204	40054	80101	101	80000	100	80008	300	640212	80108	200	80012	200	160024	1	80000	100
80204	40054	80101	101	80000	100	80008	300	640212	80108	200	80012	200	160024	1	80000	100
80204	40054	80101	101	80000	100	80008	300	640212	80108	200	80012	200	160024	1	80000	100
80204	40054	80101	101	80000	100	80008	300	640212	80108	200	80012	200	160024	1	80000	100
80204	40054	80101	101	80000	100	80008	300	640932	80108	200	80012	200	160024	1	80000	100
80204	40101	80101	101	80000	100	80008	300	641058	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40278	80047	11	80036	10	80000	30	260456	80010	20	80000	20	160000	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640002	80010	20	80000	20	160000	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640002	80010	20	80000	20	160000	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640002	80010	20	80000	20	160000	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640002	80010	20	80000	20	160000	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640002	80010	20	80000	20	160000	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640002	80010	20	80000	20	160138	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640002	80010	20	80000	20	160000	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640002	80010	20	80000	20	160000	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640002	80010	20	80000	20	160000	1	80000	10

LDR (register, lsl, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations