Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (register, lsl, S)

Test 1: uops

Code:

  ldr s0, [x6, x7, lsl #2]
  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10057921031110301000812810001000200011000
10045511001110001000806610001000200011000
10045511001110001000798210001000200011000
10045431001110001000798210001000200011000
10045451001110001000798210001000200011000
10045431001110001000816410001000200011000
10045431001110001000816410001000200011000
10045431001110001000798210001000200011000
10045431001110001000798210001000200011000
10045431001110001000798210001000200011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, x7, lsl #2]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502051001606010840101100061000130130100151000326692211045567107074250109302101000410004602242000810004400011000040100
502041000696010340101100021000030103100031000326699051045821107103950109302101000410004602202000810004400011000040100
502041000516010340101100021000030103100031000426692931045651107082550110302121000410004602242000810004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602242000810004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602242000810004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602242000810004400011000040100
502041000496010340101100021000030103100031001526698731045859107104150164302501001710017602242000810004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602242000810004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602242000810004400011000040100
502051001476011240107100041000130133100151000426692661045640107081450110302121000410004602242000810004400011000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
500251001556001840011100061000130040100151000326692581046894107193550019300301000410004600202000010000400011000040010
500241000476001340011100021000030010100001000026709291047622107264050010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026693091046924107196150010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026701461047284107230850010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026693901046957107199450010300201000010000600202000010000400011000040010
586141347586783444945100081288134848100151000026696161047004107204550010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001001126719441048016107305650063300581001210013600202000010000400011000040010
500241000486001340011100021000030010100001000326693121046877107194150019300301000410004600202000010000400011000040010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, x7, lsl #2]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
5020510015260108401011000610001301301001510003266918310454951070676501093021010004100046022420008100044000110000040100
5020410004960103401011000210000301031000310003266908610455121070687501093021010004100046030220032100174000710000040100
5020410004760103401011000210000301031000310003266893310453901070573501093021010004100046022420008100044000110000040100
5020410004060102401011000110000301031000310004266902310455411070715501103021210004100046022420008100044000110000040100
5020410004060102401011000110000301031000310004266902310455411070715501103021210004100046022420008100044000110000040100
5020410004060102401011000110000301031000310004266902310455411070715501103021210004100046022420008100044000110000040100
5020410004060102401011000110000301031000310004266902310455411070715501103021210004100046022420008100044000110000040100
5020510014560111401071000310001301331001510004266905010455521070726501103021210004100046022420008100044000110000040100
5020410004060102401011000110000301031000310004267193910467671071918501103021210004100046022420008100044000110000040100
5020410004060102401011000110000301031000310004266902310455411070715501103021210004100046022420008100044000110000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
500251001486001840011100061000130040100151000026692381046842107188750010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026693361046937107197250010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001001226696491047044107208250064300591001210013600202000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010
500241000506001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010

Test 4: throughput

Count: 8

Code:

  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  ldr s0, [x6, x7, lsl #2]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205401928013710180036100800083002482068010820080012200160024180000100
80204400618010510180004100800083006402128010820080012200160024180000100
80204400808010110180000100800083006406268010820080012200160144180000100
80204401108010110180000100800083006402128010820080012200160024180000100
80204400548010110180000100800083006402128010820080012200160024180000100
80204400548010110180000100800083006402128010820080012200160024180000100
80204400548010110180000100800083006402128010820080012200160024180000100
80204400548010110180000100800083006402128010820080012200160024180000100
80204400548010110180000100800083006409328010820080012200160024180000100
80204401018010110180000100800083006410588010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80025402788004711800361080000302604568001020800002016000018000010
80024400568001111800001080000306400028001020800002016000018000010
80024400468001111800001080000306400028001020800002016000018000010
80024400468001111800001080000306400028001020800002016000018000010
80024400468001111800001080000306400028001020800002016000018000010
80024400468001111800001080000306400028001020800002016000018000010
80024400468001111800001080000306400028001020800002016013818000010
80024400468001111800001080000306400028001020800002016000018000010
80024400468001111800001080000306400028001020800002016000018000010
80024400468001111800001080000306400028001020800002016000018000010