Icestorm: LDR (register, sxtw, D) measurements

Code:

  ldr d0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	652	1031	1	1030	1000	8218	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	8006	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100154	60108	40101	10006	10001	30130	10015	10014	2669544	1045628	1070865	50162	30249	10016	10017	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50205	100074	60111	40107	10003	10001	30133	10016	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669266	1045642	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100155	60018	40011	10006	10001	30040	10015	10000	2669238	1046842	1071887	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10015	2669661	1047096	1072147	50073	30070	10016	10017	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50026	100165	60031	40023	10006	10002	30073	10027	10000	2669363	1046947	1071984	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100048	60013	40011	10002	10000	30010	10000	10000	2669363	1046949	1071983	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100048	60013	40011	10002	10000	30010	10000	10000	2669336	1046937	1071974	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100050	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50025	100079	60022	40017	10004	10001	30043	10015	10000	2669795	1047134	1072166	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100146	60108	40101	10006	10001	30130	10015	10003	2669124	1045470	1070650	50109	30210	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669293	1045654	1070825	50110	30212	10004	10004	60220	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60378	20058	10030	40011	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045642	1070816	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60300	20034	10017	40005	10000	40100
50204	100082	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10028	2670908	1046298	1071569	50219	30286	10030	10029	60302	20032	10017	40007	10000	40100
50205	100121	60113	40107	10005	10001	30133	10015	10004	2669239	1045630	1070803	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100348	60018	40011	10006	10001	30040	10015	10004	2669437	1047022	1072062	50020	30032	10004	10004	60044	20008	10004	40001	10000	40010
50024	100049	60013	40011	10002	10000	30013	10003	10004	2669167	1046912	1071952	50020	30032	10004	10004	60044	20008	10004	40001	10000	40010
50024	100042	60012	40011	10001	10000	30013	10003	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100103	60012	40011	10001	10000	30010	10000	10000	2669228	1046891	1071928	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100043	60012	40011	10001	10000	30010	10000	10000	2669282	1046914	1071951	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100045	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010

Test 4: throughput

Count: 8

Code:

  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]
  ldr d0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40306	80135	101	80034	100	80008	300	280188	80108	200	80012	200	160024	1	80000	100
80205	40105	80136	101	80035	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40054	80101	101	80000	100	80010	300	641970	80110	200	80014	200	160024	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640374	80108	200	80012	200	160024	1	80000	100
80204	40048	80101	101	80000	100	80059	300	551779	80159	200	80072	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640410	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40168	80134	101	80033	100	80008	300	640284	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640320	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40253	80045	11	80034	10	80000	30	320218	80010	20	80000	20	160000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	10
80024	40045	80011	11	80000	10	80057	30	333435	80067	20	80069	20	160000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	640052	80010	20	80000	20	160000	1	80000	10
80024	40083	80017	11	80006	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40052	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640090	80010	20	80000	20	160000	1	80000	10

LDR (register, sxtw, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations