Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (register, sxtw, Q)

Test 1: uops

Code:

  ldr q0, [x6, w7, sxtw]
  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056561031110301000816410001000200011000
10045511001110001000816410001000200011000
10045511001110001000816410001000200011000
10045511001110001000816410001000200011000
10045511001110001000816410001000200011000
10045511001110001000816410001000200011000
10045511001110001000816410001000200011000
10045511001110001000816410001000200011000
10045511001110001000816410001000200011000
10045511001110001000816410001000200011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502051001506010840101100061000130130100151000326691221045467107065050109302101000410004602242000810004400011000040100
502041000476010340101100021000030103100031000426692121045618107079250110302121000410004602242000810004400011000040100
502041000476010340101100021000030103100031000426692121045618107079250110302121000410004602242000810004400011000040100
502041000476010340101100021000030103100031001526695461045726107094350166302511001710017602242000810004400011000040100
502051000816011240107100041000130133100161000426692391045629107080350110302121000410004602242000810004400011000040100
502041000476010340101100021000030103100031000426692121045618107079250110302121000410004602242000810004400011000040100
502041000476010340101100021000030103100031000426692121045618107079250110302121000410004602242000810004400011000040100
502041000476010340101100021000030103100031000426692121045618107079250110302121000410004602242000810004400011000040100
502041000476010340101100021000030103100031000426692121045618107079250110302121000410004602242000810004400011000040100
502041000476010340101100021000030103100031000426692121045618107079250110302121000410004602242000810004400011000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
500251001456001740011100051000130040100151000326692581046894107193550019300301000410004600202000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010
500241001176001340011100021000030010100001000026696331047063107209750010300201000010000600202000010000400011000040010
500241000526001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010
500251000796002240017100041000130043100151000026694711046990107202750010300201000010000600202000010000400011000040010
500241000536001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010
500241000536001340011100021000030010100001000026695251047016107205350010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026694171046973107200850010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600202000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000601142003410016400051000040010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502051001456010840101100061000130130100151000326691241045470107065050109302101000410004602202000810004400011000040100
502051000776011140105100041000230133100151000326691671045545107072050109302101000410004602242000810004400011000040100
502041001516010340101100021000030103100031000426693471045646107094750111302121000510004602202000810004400011000040100
502041000516010340101100021000030103100031000426692661045640107081450110302121000410004602242000810004400011000040100
502041000496010340101100021000030103100031000426692931045651107082550110302121000410004602242000810004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602242000810004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602242000810004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602242000810004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602242000810004400011000040100
502051000796011140105100041000230133100151000426692661045640107081450110302121000410004602242000810004400011000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0043

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
500251002456001940011100071000130040100151000326693181046921107196350019300301000410004600202000010000400011000040010
500241000406001240011100011000030010100001000026692281046891107192850010300201000010000600202000010000400011000040010
500241000426001240011100011000030010100001000026692011046882107191950010300201000010000600202000010000400011000040010
500241000406001240011100011000030010100001000026692821046914107195150010300201000010000600202000010000400011000040010
500241000406001240011100011000030010100001000026692011046880107191750010300201000010000600202000010000400011000040010
500241000406001240011100011000030010100001000026690931046836107187350010300201000010000600202000010000400011000040010
500241000406001240011100011000030010100001000026690931046836107187350010300201000010000600202000010000400011000040010
500241000406001240011100011000030010100001000026695251047021107205850010300201000010000600202000010000400011000040010
500241001396002540019100041000230043100131000026690931046836107187350010300201000010000600202000010000400011000040010
500241000406001240011100011000030010100001000026692281046896107193350010300201000010000600202000010000400011000040010

Test 4: throughput

Count: 8

Code:

  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205403428013510180034100800083002560608010820080012200160024180000100
80204400578010110180000100800083006401908010820080012200160024180000100
80204400538010110180000100800083006400288010820080012200160028180000100
80204400478010110180000100800083006400288010820080012200160024180000100
80204400478010110180000100800593006040318015920080072200160024180000100
80204400478010110180000100800083006400288010820080012200160024180000100
80204400478010110180000100800083006400288010820080012200160024180000100
80204401078010110180000100800083006401368010820080012200160024180000100
80204400508010110180000100800083006401368010820080012200160024180000100
80204400478010110180000100800083006400288010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80025402878004511800341080010306402068002020800142016000018000010
80024400518001111800001080000306401648001020800002016000018000010
80024400518001111800001080000306401648001020800002016000018000010
80024400518001111800001080000306401648001020800002016000018000010
80024400518001111800001080000306401648001020800002016000018000010
80024400518001111800001080000306401648001020800002016000018000010
80024400518001111800001080000306401648001020800002016000018000010
80024400518001111800001080000306401648001020800002016000018000010
80024400518001111800001080000306401648001020800002016000018000010
80024400518001111800001080000306401648001020800002016000018000010