Icestorm: LDR (register, sxtw, Q) measurements

Code:

  ldr q0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	656	1031	1	1030	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100150	60108	40101	10006	10001	30130	10015	10003	2669122	1045467	1070650	50109	30210	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10015	2669546	1045726	1070943	50166	30251	10017	10017	60224	20008	10004	40001	10000	40100
50205	100081	60112	40107	10004	10001	30133	10016	10004	2669239	1045629	1070803	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100145	60017	40011	10005	10001	30040	10015	10003	2669258	1046894	1071935	50019	30030	10004	10004	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100117	60013	40011	10002	10000	30010	10000	10000	2669633	1047063	1072097	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100052	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50025	100079	60022	40017	10004	10001	30043	10015	10000	2669471	1046990	1072027	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100053	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100053	60013	40011	10002	10000	30010	10000	10000	2669525	1047016	1072053	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669417	1046973	1072008	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60114	20034	10016	40005	10000	40010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100145	60108	40101	10006	10001	30130	10015	10003	2669124	1045470	1070650	50109	30210	10004	10004	60220	20008	10004	40001	10000	40100
50205	100077	60111	40105	10004	10002	30133	10015	10003	2669167	1045545	1070720	50109	30210	10004	10004	60224	20008	10004	40001	10000	40100
50204	100151	60103	40101	10002	10000	30103	10003	10004	2669347	1045646	1070947	50111	30212	10005	10004	60220	20008	10004	40001	10000	40100
50204	100051	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50205	100079	60111	40105	10004	10002	30133	10015	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0043

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100245	60019	40011	10007	10001	30040	10015	10003	2669318	1046921	1071963	50019	30030	10004	10004	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669228	1046891	1071928	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669201	1046882	1071919	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669282	1046914	1071951	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669201	1046880	1071917	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669525	1047021	1072058	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100139	60025	40019	10004	10002	30043	10013	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669228	1046896	1071933	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010

Test 4: throughput

Count: 8

Code:

  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]
  ldr q0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40342	80135	101	80034	100	80008	300	256060	80108	200	80012	200	160024	1	80000	100
80204	40057	80101	101	80000	100	80008	300	640190	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640028	80108	200	80012	200	160028	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80059	300	604031	80159	200	80072	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	160024	1	80000	100
80204	40107	80101	101	80000	100	80008	300	640136	80108	200	80012	200	160024	1	80000	100
80204	40050	80101	101	80000	100	80008	300	640136	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40287	80045	11	80034	10	80010	30	640206	80020	20	80014	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	160000	1	80000	10

LDR (register, sxtw, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations