Icestorm: LDR (register, sxtw, S) measurements

Code:

  ldr s0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	659	1031	1	1030	1000	8218	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	7998	1000	1000	2000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100154	60108	40101	10006	10001	30130	10015	10003	2669176	1045489	1070672	50109	30210	10004	10004	60224	20008	10004	40001	10000	40100
50205	100084	60112	40107	10004	10001	30133	10015	10003	2669356	1045625	1070798	50109	30210	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50205	100081	60112	40107	10004	10001	30133	10015	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100157	60018	40011	10006	10001	30040	10015	10004	2669333	1046979	1072020	50020	30032	10004	10004	60020	20000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50025	100088	60023	40017	10005	10001	30043	10016	10000	2669298	1046867	1071913	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2671361	1047786	1072816	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100057	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60198	20058	10030	40013	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10012	2671396	1047810	1072816	50064	30058	10013	10013	60020	20000	10000	40001	10000	40010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, w7, sxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100155	60108	40101	10006	10001	30130	10015	10015	2671803	1046635	1071800	50163	30249	10016	10017	60220	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10003	2669167	1045545	1070720	50109	30210	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100071	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50206	100172	60121	40113	10006	10002	30163	10027	10004	2669266	1045642	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100054	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100050	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100158	60018	40011	10006	10001	30040	10015	10049	2675683	1049500	1074588	50243	30174	10049	10052	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100057	60013	40011	10002	10000	30010	10000	10000	2670632	1047506	1072543	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669336	1046937	1071972	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100434	60065	40043	10014	10008	30142	10052	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60114	20032	10017	40007	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60326	20098	10052	40033	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60098	20026	10013	40005	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010

Test 4: throughput

Count: 8

Code:

  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]
  ldr s0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40164	80137	101	80036	100	80008	300	256242	80108	200	80012	200	160024	1	80000	100
80204	40057	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80058	300	315450	80158	200	80071	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80010	300	642762	80110	200	80014	200	160024	1	80000	100
80204	40059	80101	101	80000	100	80008	300	640698	80108	200	80012	200	160024	1	80000	100
80204	40057	80101	101	80000	100	80008	300	248022	80108	200	80012	200	160024	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40599	80047	11	80036	10	80008	30	320188	80018	20	80012	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80057	30	640593	80067	20	80070	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10

LDR (register, sxtw, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations