Icestorm: LDR (register, uxtw, D) measurements

Code:

  ldr d0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	679	1031	1	1030	1000	8164	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	544	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7998	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7653	1000	1000	2000	1	1000
1004	553	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	2000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, w7, uxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50205	100154	60108	40101	10006	10001	30130	10015	10003	2669124	1045470	1070650	50109	30210	10004	10004	60220	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60294	20034	10016	40005	10000	0	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10016	2669367	1045667	1070907	50165	30251	10017	10017	60224	20008	10004	40001	10000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50025	100148	60018	40011	10006	10001	30040	10015	10016	2669554	1046999	1072070	50074	30067	10017	10016	60044	20008	10004	40001	10000	0	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100043	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669120	1046848	1071885	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50025	100070	60020	40015	10003	10002	30043	10015	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50025	100116	60020	40015	10003	10002	30043	10015	10000	2669309	1046925	1071961	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, w7, uxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50205	100149	60108	40101	10006	10001	30130	10015	10004	2669266	1045640	1070814	50110	30212	10004	10004	60220	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669401	1045700	1070874	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100050	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10015	2669606	1045756	1070978	50166	30251	10017	10017	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100153	60018	40011	10006	10001	30040	10015	10003	2669123	1046839	1071880	50019	30030	10004	10004	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100122	60013	40011	10002	10000	30010	10000	10017	2670030	1047257	1072316	50076	30071	10018	10017	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10015	2669963	1047225	1072268	50074	30070	10017	10017	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50025	100074	60021	40017	10003	10001	30043	10016	10000	2669201	1046880	1071917	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010

Test 4: throughput

Count: 8

Code:

  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]
  ldr d0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40194	80137	101	80036	100	80008	300	248188	80108	200	80012	200	160028	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80059	300	395597	80159	200	80072	200	160024	1	80000	100
80204	40054	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40239	80047	11	80036	10	80008	30	320006	80018	20	80012	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	641366	80010	20	80000	20	160000	1	80000	10
80024	40057	80011	11	80000	10	80000	30	640414	80010	20	80000	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	160000	1	80000	10

LDR (register, uxtw, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations