Icestorm: LDR (register, uxtw, Q) measurements

Code:

  ldr q0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	657	1031	1	1030	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	2000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, w7, uxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100155	60108	40101	10006	10001	30130	10015	10003	2669139	1045418	1070606	50109	30210	10004	10004	60220	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50205	100097	60114	40109	10004	10001	30135	10016	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100060	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	20008	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50026	100186	60027	40017	10008	10002	30070	10027	10004	2669123	1046836	1071882	50020	30032	10004	10004	60020	20000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669120	1046848	1071885	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100107	60013	40011	10002	10000	30010	10000	10000	2669255	1046903	1071940	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60114	20034	10016	40005	10000	40010
50024	100044	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010
50025	100122	60021	40015	10004	10002	30043	10015	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	20000	10000	40001	10000	40010

Test 3: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, w7, uxtw]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50206	100327	60116	40105	10008	10003	30160	10027	10003	2668988	1045416	1070597	50109	30210	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669158	1045598	1070770	50110	30212	10004	10004	60528	20106	10055	40033	10000	0	40100
50204	100043	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60294	20032	10017	40007	10000	0	40100
50204	100057	60103	40101	10002	10000	30103	10004	10028	2672281	1046756	1071943	50220	30286	10029	10029	60224	20008	10004	40001	10000	0	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100
50204	100053	60102	40101	10001	10000	30103	10003	10028	2672358	1046867	1072197	50222	30285	10029	10029	60224	20008	10004	40001	10000	0	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	20008	10004	40001	10000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50025	100163	60018	40011	10006	10001	30040	10015	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60118	20034	10017	40007	10000	0	40010
50024	100058	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10016	2669478	1047018	1072076	50074	30067	10017	10016	61768	21229	10030	40700	10596	3	40940
50024	100042	60012	40011	10001	10000	30013	10003	10000	2669130	1046798	1071843	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	20000	10000	40001	10000	0	40010
50024	100042	60012	40011	10001	10000	30010	10000	10012	2671748	1047883	1072937	50064	30059	10012	10013	60020	20000	10000	40001	10000	0	40010

Test 4: throughput

Count: 8

Code:

  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]
  ldr q0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40193	80131	101	80030	100	80010	300	640206	0	80110	200	80014	0	200	160028	1	80000	100
80204	40054	80101	101	80000	100	80008	300	640284	0	80108	200	80012	0	200	160024	1	80000	100
80204	40059	80101	101	80000	100	80008	300	640302	0	80108	200	80012	0	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	0	80108	200	80012	0	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	0	80108	200	80012	0	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	0	80108	200	80012	0	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	0	80108	200	80012	0	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	0	80108	200	80012	0	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	0	80108	200	80012	0	200	160024	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	0	80108	200	80012	0	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	40260	80045	11	80034	10	80000	30	640218	80010	20	80000	20	160000	1	80000	0	10
80024	40054	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160142	1	80000	0	10
80024	40088	80011	11	80000	10	80000	30	640052	80010	20	80000	20	160000	1	80000	0	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	0	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160138	1	80000	0	10
80024	40055	80011	11	80000	10	80000	30	640126	80010	20	80000	20	160000	1	80000	0	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	0	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	0	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	0	10
80024	40050	80011	11	80000	10	80000	30	639998	80010	20	80000	20	160000	1	80000	0	10

LDR (register, uxtw, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations