Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (unsigned offset, D)

Test 1: uops

Code:

  ldr d0, [x6, #8]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056521031110301000816410001000100011000
10045511001110001000798210001000100011000
10045431001110001000798210001000100011000
10045431001110001000798210001000100011000
10045431001110001000798210001000100011000
10045431001110001000798210001000100011000
10045431001110001000798210001000100011000
10045511001110001000798210001000100011000
10045431001110001000798210001000100011000
10045431001110001000798210001000100011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, #8]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502051001526010840101100061000130130100141000426692211045564107074450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426693741045684107085850110302121000410004602241000410004400011000040100
502051000796011140105100041000230133100151001626698491045864107103450164302511001610017603441002510024400121000040100
502041000606010340101100021000030103100031001526704741046114107127750165302471001610016602241000410004400011000040100
502051001276011240107100041000130133100161000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502051000816011240107100041000130130100121000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
5002510015560018400111000610001300401001410004266925810468911071937500203003210004100046002010000100004000110000040010
5002410004760013400111000210000300101000010000266928210469131071950500103002010000100006002010000100004000110000040010
5002410004760013400111000210000300101000010000266928210469131071950500103002010000100006002010000100004000110000040010
5002410004760013400111000210000300101000010000266928210469131071950500103002010000100006002010000100004000110000040010
5002410004760013400111000210000300101000010000266928210469131071950500103002010000100006002010000100004000110000040010
5002410004760013400111000210000300101000010000266928210469131071950500103002010000100006002010000100004000110000040010
5002410004760013400111000210000300101000010000266928210469131071950500103002010000100006002010000100004000110000040010
5002410004760013400111000210000300101000010000266933610469351071972500103002010000100006002010000100004000110000040010
5002410004760013400111000210000300101000010000266928210469131071950500103002010000100006002010000100004000110000040010
5002410004760013400111000210000300101000010000266928210469131071950500103002010000100006002010000100004000110000040010

Test 3: throughput

Count: 8

Code:

  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540172801351018003410080008300248188801082008001220080012180000100
8020440059801051018000410080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440062801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640302801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540277800451180034108000830400188800182080012208000018000010
8002440051800111180000108000030640164800102080000208000018000010
8002440051800111180000108000030640164800102080000208000018000010
8002440162800111180000108000030640326800102080000208006918000010
8002440063800111180000108000030640218800102080000208000018000010
8002440051800111180000108000030640164800102080000208000018000010
8002440054800111180000108000030640164800102080000208000018000010
8002440051800111180000108000030640164800102080000208000018000010
8002440051800111180000108000030640164800102080000208001218000010
8002440054800111180000108000030640254800102080000208000018000010