Icestorm: LDR (unsigned offset, D) measurements

Code:

  ldr d0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	652	1031	1	1030	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	7982	1000	1000	1000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr d0, [x6, #8]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100152	60108	40101	10006	10001	30130	10014	10004	2669221	1045564	1070744	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669374	1045684	1070858	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50205	100079	60111	40105	10004	10002	30133	10015	10016	2669849	1045864	1071034	50164	30251	10016	10017	60344	10025	10024	40012	10000	40100
50204	100060	60103	40101	10002	10000	30103	10003	10015	2670474	1046114	1071277	50165	30247	10016	10016	60224	10004	10004	40001	10000	40100
50205	100127	60112	40107	10004	10001	30133	10016	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50205	100081	60112	40107	10004	10001	30130	10012	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50025	100155	60018	40011	10006	10001	30040	10014	10004	2669258	1046891	1071937	50020	30032	10004	10004	60020	10000	10000	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010

Test 3: throughput

Count: 8

Code:

  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]
  ldr d0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40172	80135	101	80034	100	80008	300	248188	80108	200	80012	200	80012	1	80000	100
80204	40059	80105	101	80004	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40062	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640302	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640194	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40277	80045	11	80034	10	80008	30	400188	80018	20	80012	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40162	80011	11	80000	10	80000	30	640326	80010	20	80000	20	80069	1	80000	10
80024	40063	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640164	80010	20	80000	20	80012	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640254	80010	20	80000	20	80000	1	80000	10

LDR (unsigned offset, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations