Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (unsigned offset, Q)

Test 1: uops

Code:

  ldr q0, [x6, #8]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056521031110301000816410001000100011000
10045511001110001000818210001000100011000
10045521001110001000816410001000100011000
10045511001110001000816410001000100011000
10045511001110001000816410001000100011000
10045511001110001000816410001000100011000
10045511001110001000816410001000100011000
10045511001110001000816410001000100011000
10045511001110001000816410001000100011000
10045511001110001000816410001000100011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, #8]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502051001486010840101100061000130130100141000426692211045564107074450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031001426696331045761107093550162302471001610017602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502071002056012940117100081000430193100391000426693601045642107083050110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426698331045883107105150110302121000410004602241000410004400011000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
500251001506001840011100061000130040100141000426691231046836107188250020300321000410004600201000010000400011000040010
500241000506001340011100021000030010100001000026693361046935107197250010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001000026693361046935107197250010300201000010000600201000010000400011000040010
500241000496001340011100021000030010100001000026693901046959107199650010300201000010000600201000010000400011000040010
500241000506001340011100021000030010100001000026693361046935107197250010300201000010000600201000010000400011000040010
500241000496001340011100021000030010100001000026693361046935107197250010300201000010000601221001610017400071000040010
500241000746001340011100021000030010100001000026693901046957107199450010300201000010000600201000010000400011000040010
500241000516001340011100021000030010100001000026693361046935107197250010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001000026693361046935107197250010300201000010000601141001710016400051000040010
50024100052600134001110002100003001010000961025440699981931021521478762880196209557601181001610016400081000040010

Test 3: throughput

Count: 8

Code:

  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540186801351018003410080008300248242801082008001220080012180000100
8020440056801011018000010080008300640248801082008001220080012180000100
8020440056801011018000010080008300640248801082008001220080012180000100
8020440056801011018000010080008300640248801082008001220080012180000100
8020440149801011018000010080008300640082801082008001220080012180000100
8020440056801011018000010080008300640338801082008001220080012180000100
8020440062801011018000010080008300640356801082008001220080012180000100
8020440053801011018000010080008300640500801082008001220080012180000100
8020440047801011018000010080008300640248801082008001220080012180000100
8020440056801011018000010080008300640248801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002640339800711180060108000830640788800182080012208000018000010
8002440073800111180000108000030644394800102080000208001418000010
8002440100800111180000108000030640452800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010