Icestorm: LDR (unsigned offset, Q) measurements

Code:

  ldr q0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	652	1031	1	1030	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8182	1000	1000	1000	1	1000
1004	552	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr q0, [x6, #8]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100148	60108	40101	10006	10001	30130	10014	10004	2669221	1045564	1070744	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10014	2669633	1045761	1070935	50162	30247	10016	10017	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50207	100205	60129	40117	10008	10004	30193	10039	10004	2669360	1045642	1070830	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669833	1045883	1071051	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100150	60018	40011	10006	10001	30040	10014	10004	2669123	1046836	1071882	50020	30032	10004	10004	60020	10000	10000	40001	10000	40010
50024	100050	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669390	1046959	1071996	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100050	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60122	10016	10017	40007	10000	40010
50024	100074	60013	40011	10002	10000	30010	10000	10000	2669390	1046957	1071994	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100051	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60114	10017	10016	40005	10000	40010
50024	100052	60013	40011	10002	10000	30010	10000	9610	2544069	998193	1021521	47876	28801	9620	9557	60118	10016	10016	40008	10000	40010

Test 3: throughput

Count: 8

Code:

  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]
  ldr q0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40186	80135	101	80034	100	80008	300	248242	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40149	80101	101	80000	100	80008	300	640082	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640338	80108	200	80012	200	80012	1	80000	100
80204	40062	80101	101	80000	100	80008	300	640356	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	80000	100	80008	300	640500	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80026	40339	80071	11	80060	10	80008	30	640788	80018	20	80012	20	80000	1	80000	10
80024	40073	80011	11	80000	10	80000	30	644394	80010	20	80000	20	80014	1	80000	10
80024	40100	80011	11	80000	10	80000	30	640452	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10

LDR (unsigned offset, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations