Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (unsigned offset, S)

Test 1: uops

Code:

  ldr s0, [x6, #8]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056681031110301000816410001000100011000
10045511001110001000816410001000100011000
10045511001110001000816410001000100011000
10045511001110001000816410001000100011000
10045511001110001000816410001000100011000
10045511001110001000816410001000100011000
10045511001110001000816410001000100011000
10045541001110001000816410001000100011000
10045511001110001000816410001000100011000
10045511001110001000816410001000100011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, #8]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
5020510014860108401011000610001301301001410004266917410454851070671501103021210004100046022410004100044000110000040100
5020410007160104401011000310000301031000310004266923910456291070803501103021210004100046022410004100044000110000040100
5020410004060102401011000110000301031000310004266902310455411070715501103021210004100046022410004100044000110000040100
5020410004060102401011000110000301031000310015266939010456751070902501643025010017100176022410004100044000110000040100
5020410004560102401011000110000301031000310004266907710455631070737501103021210004100046022410004100044000110000040100
5020410004060102401011000110000301031000310004266902310455411070715501103021210004100046029410016100174000710000040100
5020410004060102401011000110000301031000310004266902310455411070715501103021210004100046022410004100044000110000040100
5020410004060102401011000110000301031000310004266902310455411070715501103021210004100046022410004100044000110000040100
5020410004060102401011000110000301031000310004266902310455411070715501103021210004100046022410004100044000110000040100
5020410004060102401011000110000301031000310004266902310455411070715501103021210004100046022410004100044000110000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
5002510016060018400111000610001300401001410004266989610472091072249500203003210004100046004410004100044000110000040010
5002410004760013400111000210000300131000310004266930210469671072007500203003210004100046002010000100004000110000040010
5002410004760013400111000210000300101000010000266928210469131071950500103002010000100006002010000100004000110000040010
5002410004760013400111000210000300101000010000266928210469131071950500103002010000100006002010000100004000110000040010
5002410004760013400111000210000300101000010015267182610480051073049500743007010017100176002010000100004000110000040010
5002410004060012400111000110000300101000010000266909310468361071873500103002010000100006002010000100004000110000040010
5002410004060012400111000110000300101000010000266917410468721071906500103002010000100006002010000100004000110000040010
50024100040600124001110001100003001010000100292671325104775410728155012930102100301002851964200545323300871123517730835
5002510007460021400171000310001300431001510004267003210471861072240500203003210004100046002010000100004000110000040010
5002510013360022400171000410001300431001510000266914710468581071895500103002010000100006002010000100004000110000040010

Test 3: throughput

Count: 8

Code:

  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540161801331018003210080008300248242801082008001220080012180000100
8020440056801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540228800471180036108000030601016800102080000208000018000010
8002440069800111180000108000030640308800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010