Icestorm: LDR (unsigned offset, S) measurements

Code:

  ldr s0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	668	1031	1	1030	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000
1004	551	1001	1	1000	1000	8164	1000	1000	1000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldr s0, [x6, #8]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50205	100148	60108	40101	10006	10001	30130	10014	10004	2669174	1045485	1070671	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100071	60104	40101	10003	10000	30103	10003	10004	2669239	1045629	1070803	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10015	2669390	1045675	1070902	50164	30250	10017	10017	60224	10004	10004	40001	10000	0	40100
50204	100045	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60294	10016	10017	40007	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	10004	10004	40001	10000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50025	100160	60018	40011	10006	10001	30040	10014	10004	2669896	1047209	1072249	50020	30032	10004	10004	60044	10004	10004	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30013	10003	10004	2669302	1046967	1072007	50020	30032	10004	10004	60020	10000	10000	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100047	60013	40011	10002	10000	30010	10000	10015	2671826	1048005	1073049	50074	30070	10017	10017	60020	10000	10000	40001	10000	0	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669093	1046836	1071873	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100040	60012	40011	10001	10000	30010	10000	10000	2669174	1046872	1071906	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100040	60012	40011	10001	10000	30010	10000	10029	2671325	1047754	1072815	50129	30102	10030	10028	51964	20054	5323	30087	11235	177	30835
50025	100074	60021	40017	10003	10001	30043	10015	10004	2670032	1047186	1072240	50020	30032	10004	10004	60020	10000	10000	40001	10000	0	40010
50025	100133	60022	40017	10004	10001	30043	10015	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010

Test 3: throughput

Count: 8

Code:

  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  ldr s0, [x6, #8]
  ldr s0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40161	80133	101	80032	100	80008	300	248242	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40228	80047	11	80036	10	80000	30	601016	80010	20	80000	20	80000	1	80000	10
80024	40069	80011	11	80000	10	80000	30	640308	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640218	80010	20	80000	20	80000	1	80000	10

LDR (unsigned offset, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations