Icestorm: LDUR (D) measurements

Code:

  ldur d0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	654	1031	1	1030	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8272	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldur d0, [x6, #1]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100282	60108	40101	10006	10001	30130	10014	10016	2669400	1045622	1070799	50164	30251	10016	10017	60224	10004	10004	40001	10000	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669023	1045541	1070715	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669077	1045565	1070738	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100041	60102	40101	10001	10000	30103	10003	10004	2669158	1045599	1070771	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100074	60104	40101	10003	10000	30103	10003	10004	2669042	1045433	1070619	50110	30212	10004	10004	60292	10016	10016	40006	10000	40100
50205	100077	60111	40107	10003	10001	30133	10016	10004	2669536	1045757	1070928	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60294	10016	10017	40007	10000	40100
50204	100051	60102	40101	10001	10000	30103	10003	10004	2669077	1045563	1070737	50110	30212	10004	10004	60294	10017	10016	40005	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50025	100636	60018	40011	10006	10001	30040	10014	10000	2669252	1046792	1071843	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100049	60013	40011	10002	10000	30010	10000	10015	2669720	1047113	1072168	50074	30070	10017	10017	60020	10000	10000	40001	10000	0	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669444	1046979	1072016	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100062	60013	40011	10002	10000	30010	10000	10016	2670631	1047502	1072539	50074	30069	10017	10017	60020	10000	10000	40001	10000	0	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	0	40010

Test 3: throughput

Count: 8

Code:

  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80206	40468	80168	101	80067	100	80008	300	297202	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80059	300	640658	80159	200	80072	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640120	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640012	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640012	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640012	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640012	80108	200	80012	200	80012	1	80000	100
80204	40051	80101	101	80000	100	80008	300	640120	80108	200	80012	200	80012	1	80000	100
80204	40050	80101	101	80000	100	80008	300	640012	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640012	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40516	80045	11	80034	10	80000	30	639998	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	639998	80010	20	80000	20	80000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	80000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	80000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	80000	1	80000	10
80024	40045	80011	11	80000	10	80059	30	497231	80069	20	80071	20	80000	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640142	80010	20	80000	20	80000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	642014	80010	20	80000	20	80000	1	80000	10
80024	40088	80011	11	80000	10	80000	30	640340	80010	20	80000	20	80000	1	80000	10

LDUR (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations