Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDUR (D)

Test 1: uops

Code:

  ldur d0, [x6, #1]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056541031110301000821810001000100011000
10045541001110001000821810001000100011000
10045541001110001000821810001000100011000
10045541001110001000821810001000100011000
10045541001110001000821810001000100011000
10045541001110001000821810001000100011000
10045541001110001000821810001000100011000
10045541001110001000827210001000100011000
10045541001110001000821810001000100011000
10045541001110001000821810001000100011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldur d0, [x6, #1]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502051002826010840101100061000130130100141001626694001045622107079950164302511001610017602241000410004400011000040100
502041000406010240101100011000030103100031000426690231045541107071550110302121000410004602241000410004400011000040100
502041000406010240101100011000030103100031000426690231045541107071550110302121000410004602241000410004400011000040100
502041000406010240101100011000030103100031000426690771045565107073850110302121000410004602241000410004400011000040100
502041000416010240101100011000030103100031000426691581045599107077150110302121000410004602241000410004400011000040100
502041000746010440101100031000030103100031000426690421045433107061950110302121000410004602921001610016400061000040100
502051000776011140107100031000130133100161000426695361045757107092850110302121000410004602241000410004400011000040100
502041000426010240101100011000030103100031000426690771045563107073750110302121000410004602241000410004400011000040100
502041000426010240101100011000030103100031000426690771045563107073750110302121000410004602941001610017400071000040100
502041000516010240101100011000030103100031000426690771045563107073750110302121000410004602941001710016400051000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
5002510063660018400111000610001300401001410000266925210467921071843500103002010000100006002010000100004000110000040010
5002410004960013400111000210000300101000010000266933610469351071972500103002010000100006002010000100004000110000040010
5002410004960013400111000210000300101000010000266933610469351071972500103002010000100006002010000100004000110000040010
5002410004960013400111000210000300101000010000266933610469351071972500103002010000100006002010000100004000110000040010
5002410004960013400111000210000300101000010000266933610469351071972500103002010000100006002010000100004000110000040010
5002410004960013400111000210000300101000010015266972010471131072168500743007010017100176002010000100004000110000040010
5002410004960013400111000210000300101000010000266944410469791072016500103002010000100006002010000100004000110000040010
5002410006260013400111000210000300101000010016267063110475021072539500743006910017100176002010000100004000110000040010
5002410004960013400111000210000300101000010000266933610469351071972500103002010000100006002010000100004000110000040010
5002410004960013400111000210000300101000010000266933610469351071972500103002010000100006002010000100004000110000040010

Test 3: throughput

Count: 8

Code:

  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  ldur d0, [x6, #1]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020640468801681018006710080008300297202801082008001220080012180000100
8020440045801011018000010080059300640658801592008007220080012180000100
8020440049801011018000010080008300640120801082008001220080012180000100
8020440045801011018000010080008300640012801082008001220080012180000100
8020440045801011018000010080008300640012801082008001220080012180000100
8020440045801011018000010080008300640012801082008001220080012180000100
8020440045801011018000010080008300640012801082008001220080012180000100
8020440051801011018000010080008300640120801082008001220080012180000100
8020440050801011018000010080008300640012801082008001220080012180000100
8020440045801011018000010080008300640012801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540516800451180034108000030639998800102080000208000018000010
8002440054800111180000108000030639998800102080000208000018000010
8002440045800111180000108000030639998800102080000208000018000010
8002440045800111180000108000030639998800102080000208000018000010
8002440045800111180000108000030639998800102080000208000018000010
8002440045800111180000108005930497231800692080071208000018000010
8002440056800111180000108000030640142800102080000208000018000010
8002440045800111180000108000030639998800102080000208000018000010
8002440054800111180000108000030642014800102080000208000018000010
8002440088800111180000108000030640340800102080000208000018000010