Icestorm: LDUR (Q) measurements

Code:

  ldur q0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	655	1031	1	1030	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000
1004	554	1001	1	1000	1000	8218	1000	1000	1000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ldur q0, [x6, #1]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100152	60108	40101	10006	10001	30130	10014	10004	2669174	1045485	1070671	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60292	10017	10016	40005	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60300	10017	10017	40007	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669374	1045685	1070859	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100049	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100148	60018	40011	10006	10001	30040	10014	10000	2669291	1046859	1071902	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60120	10017	10017	40005	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100047	60012	40011	10001	10000	30010	10000	10016	2669858	1047175	1072216	50074	30071	10016	10017	60020	10000	10000	40001	10000	40010
50024	100045	60012	40011	10001	10000	30010	10000	10000	2669390	1046957	1071994	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100043	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010

Test 3: throughput

Count: 8

Code:

  ldur q0, [x6, #1]
  ldur q0, [x6, #1]
  ldur q0, [x6, #1]
  ldur q0, [x6, #1]
  ldur q0, [x6, #1]
  ldur q0, [x6, #1]
  ldur q0, [x6, #1]
  ldur q0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40172	80135	101	0	80034	100	0	80008	300	248188	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	0	80000	100	0	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	0	80000	100	0	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	0	80000	100	0	80008	300	640194	80108	200	80012	200	80072	1	80000	100
80204	40053	80101	101	0	80000	100	0	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	0	80000	100	0	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	0	80000	100	0	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	0	80000	100	0	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40053	80101	101	0	80000	100	0	80008	300	640194	80108	200	80012	200	80012	1	80000	100
80204	40070	80101	101	0	80000	100	0	80008	300	640410	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40252	80041	11	80030	10	80000	30	640162	0	80010	20	80000	0	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640090	0	80010	20	80000	0	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640036	0	80010	20	80000	0	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	0	80010	20	80000	0	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	0	80010	20	80000	0	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	0	80010	20	80000	0	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	0	80010	20	80000	0	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	0	80010	20	80000	0	20	80000	1	80000	10
80025	40096	80046	11	80035	10	80059	30	645140	0	80069	20	80071	0	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	0	80010	20	80000	0	20	80000	1	80000	10

LDUR (Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations