Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MOVI (vector, 2S, lsl)

Test 1: uops

Code:

  movi v0.2s, #3, lsl #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)? int output thing (e9)? simd retires (ee)
1004552100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000

Test 2: throughput

Count: 8

Code:

  movi v0.2s, #3, lsl #8
  movi v1.2s, #3, lsl #8
  movi v2.2s, #3, lsl #8
  movi v3.2s, #3, lsl #8
  movi v4.2s, #3, lsl #8
  movi v5.2s, #3, lsl #8
  movi v6.2s, #3, lsl #8
  movi v7.2s, #3, lsl #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? simd retires (ee)? int retires (ef)
802044007580105101800040100800080300032004480110200080014200180000100
802044003580109101800080100800120300032003680108200080012200180000100
802044003480105101800040100800080300032003680108200080012200180000100
802044004480107101800060100800100300032003680108200080012200180000100
802044003480105101800040100800080300032003680108200080012200180000100
802044003480105101800040100800080300032003680108200080012200180000100
802044003480105101800040100800080300032003680108200080012200180000100
802044003480105101800040100800080300032003680108200080012200180000100
802044003480105101800040100800080300032003680108200080012200180000100
802044003480105101800040100800080300032003680108200080012200180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? simd retires (ee)? int retires (ef)
8002440147800292180008208001219311510965567132036885280458922198011220118000010
800254006980063218004220800540700320000800202008000020118000010
800244003480021218000020800000650320000800202008000020118000010
800244003480021218000020800000650320000800202008000020118000010
800244003480021218000020800000650320000800202008000020118000010
800244003480021218000020800000650320000800202008000020118000010
800244003480021218000020800000650320000800202008000020118000010
800244003480021218000020800000650320000800202008000020118000010
800244003480021218000020800000650320000800202008000020118000010
800244003480021218000020800000650320000800202008000020118000010