Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
movi v0.2s, #0
(no loop instructions)
Retires: 1.000
Issues: 0.000
Integer unit issues: 0.001
Load/store unit issues: 0.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | ? int output thing (e9) | ? simd retires (ee) |
1004 | 525 | 1 | 1 | 1 | 1000 |
1004 | 284 | 1 | 1 | 1 | 1000 |
1004 | 275 | 1 | 1 | 1 | 1000 |
1004 | 275 | 1 | 1 | 1 | 1000 |
1004 | 275 | 1 | 1 | 1 | 1000 |
1004 | 275 | 1 | 1 | 1 | 1000 |
1004 | 275 | 1 | 1 | 1 | 1000 |
1004 | 275 | 1 | 1 | 1 | 1000 |
1004 | 275 | 1 | 1 | 1 | 1000 |
1004 | 275 | 1 | 1 | 1 | 1000 |
Count: 8
Code:
movi v0.2s, #0 movi v1.2s, #0 movi v2.2s, #0 movi v3.2s, #0 movi v4.2s, #0 movi v5.2s, #0 movi v6.2s, #0 movi v7.2s, #0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.2511
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
80204 | 20315 | 101 | 101 | 100 | 300 | 100 | 200 | 200 | 1 | 80000 | 100 |
80204 | 20096 | 101 | 101 | 100 | 300 | 100 | 200 | 200 | 1 | 80000 | 100 |
80204 | 20086 | 101 | 101 | 100 | 300 | 100 | 200 | 200 | 1 | 80000 | 100 |
80204 | 20086 | 101 | 101 | 100 | 300 | 100 | 200 | 200 | 1 | 80000 | 100 |
80204 | 20086 | 101 | 101 | 100 | 300 | 100 | 200 | 200 | 1 | 80000 | 100 |
80204 | 20086 | 101 | 101 | 100 | 300 | 100 | 200 | 200 | 1 | 80000 | 100 |
80204 | 20086 | 101 | 101 | 100 | 300 | 100 | 200 | 200 | 1 | 80000 | 100 |
80204 | 20086 | 101 | 101 | 100 | 300 | 100 | 200 | 200 | 1 | 80000 | 100 |
80204 | 20086 | 101 | 101 | 100 | 300 | 100 | 200 | 200 | 1 | 80000 | 100 |
80204 | 20086 | 101 | 101 | 100 | 300 | 100 | 200 | 200 | 1 | 80000 | 100 |
Result (median cycles for code divided by count): 0.2507
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
80024 | 21893 | 21 | 21 | 20 | 69 | 20 | 20 | 20 | 11 | 80000 | 10 |
80024 | 20162 | 21 | 21 | 20 | 65 | 20 | 20 | 20 | 11 | 80000 | 10 |
80024 | 20054 | 21 | 21 | 20 | 65 | 20 | 20 | 20 | 11 | 80000 | 10 |
80024 | 20054 | 21 | 21 | 20 | 65 | 20 | 20 | 20 | 11 | 80000 | 10 |
80024 | 20054 | 21 | 21 | 20 | 65 | 20 | 20 | 20 | 11 | 80000 | 10 |
80024 | 20054 | 21 | 21 | 20 | 65 | 20 | 20 | 20 | 11 | 80000 | 10 |
80024 | 20054 | 21 | 21 | 20 | 65 | 20 | 20 | 20 | 11 | 80000 | 10 |
80024 | 20054 | 21 | 21 | 20 | 65 | 20 | 20 | 20 | 11 | 80000 | 10 |
80024 | 20054 | 21 | 21 | 20 | 65 | 20 | 20 | 20 | 11 | 80000 | 10 |
80024 | 20054 | 21 | 21 | 20 | 65 | 20 | 20 | 20 | 11 | 80000 | 10 |