Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MOVI (vector, 4H, lsl)

Test 1: uops

Code:

  movi v0.4h, #3, lsl #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)? int output thing (e9)? simd retires (ee)
1004539100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000
1004534100111000100040001000100011000

Test 2: throughput

Count: 8

Code:

  movi v0.4h, #3, lsl #8
  movi v1.4h, #3, lsl #8
  movi v2.4h, #3, lsl #8
  movi v3.4h, #3, lsl #8
  movi v4.4h, #3, lsl #8
  movi v5.4h, #3, lsl #8
  movi v6.4h, #3, lsl #8
  movi v7.4h, #3, lsl #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? simd retires (ee)? int retires (ef)
802044009680105101800040100800083003200448011020080014200180000100
802044003580109101800080100800123003200368010820080012200180000100
802044003480105101800040100800083003200368010820080012200180000100
802044003480105101800040100800083003200368010820080012200180000100
802044003480105101800040100800083003200368010820080012200180000100
802044003480105101800040100800083003201968015120080061200180000100
802044003480105101800040100800083003200368010820080012200180000100
802054006880139101800380100800503003200368010820080012200180000100
8028140459802101468004024141800523003200448011020080014200180000100
802054006980143101800420100800543003200368010820080012200180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? simd retires (ee)? int retires (ef)
800244019180027218000620800106932000080020208000020118000010
800244003480021218000020800006532000080020208000020118000010
800244003480021218000020800006532000080020208000020118000010
800244003480021218000020800006532000080020208000020118000010
800244003480021218000020800006532000080020208000020118000010
800244003480021218000020800006532000080020208000020118000010
800244003480021218000020800006632020880074208006320118000010
800244003480021218000020800006532000080020208000020118000010
800244003480021218000020800006532000080020208000020118000010
800244003480021218000020800006532000080020208000020118000010