Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MOVI (vector, 8H, zero)

Test 1: uops

Code:

  movi v0.8h, #0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)? int output thing (e9)? simd retires (ee)
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10042841111000
10042751111000
10042931111000
10042751111000
10042751111000
10042751111000
10042751111000
10042751111000
10042751111000

Test 2: throughput

Count: 8

Code:

  movi v0.8h, #0
  movi v1.8h, #0
  movi v2.8h, #0
  movi v3.8h, #0
  movi v4.8h, #0
  movi v5.8h, #0
  movi v6.8h, #0
  movi v7.8h, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2511

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? simd retires (ee)? int retires (ef)
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8020420086101101100300100200200180000100
8020420086101101100300100200200180000100
8020420086101101100300100200200180000100
8020420098101101100300100200200180000100
8020420086101101100300100200200180000100
8020420086101101100300100200200180000100
8020420086101101100300100200200180000100
8020420086101101100300100200200180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? simd retires (ee)? int retires (ef)
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