Icestorm: MOV (vector, 16B) measurements

Code:

  mov v0.16b, v1.16b
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 1.000

Issues: 0.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
8004	3876	1	1	1000	2000	1	1000
8004	2173	1	1	1000	2000	1	1000
8004	2052	1	1	1000	2000	1	1000
8004	2043	1	1	1000	2000	1	1000
8004	2043	1	1	1000	2000	1	1000
8004	2043	1	1	1000	2000	1	1000
8004	2043	1	1	1000	2000	1	1000
8004	2043	1	1	1000	2000	1	1000
8004	2043	1	1	1000	2000	1	1000
8004	2043	1	1	1000	2000	1	1000

Test 2: Latency 1->2

Chain cycles: 14

Code:

  mov v0.16b, v1.16b
  add v1.16b, v1.16b, v0.16b
  add v1.16b, v1.16b, v0.16b
  add v1.16b, v1.16b, v0.16b
  add v1.16b, v1.16b, v0.16b
  add v1.16b, v1.16b, v0.16b
  add v1.16b, v1.16b, v0.16b
  add v1.16b, v1.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 14 chain cycles): 0.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	140033	70101	101	70000	100	70000	300	3569248	70100	200	80006	200	160008	1	80000	100
80204	140033	70101	101	70000	100	70000	300	3569248	70100	200	80004	200	160008	1	80000	100
80204	140033	70101	101	70000	100	70000	300	3569248	70100	200	80004	200	160008	1	80000	100
80205	140066	70109	101	70008	100	70034	300	3569248	70100	200	80006	200	160008	1	80000	100
80204	140033	70101	101	70000	100	70000	300	3569248	70100	200	80004	200	160008	1	80000	100
80204	140033	70101	101	70000	100	70000	300	3569248	70100	200	80004	200	160008	1	80000	100
80204	140033	70101	101	70000	100	70000	300	3569248	70100	200	80004	200	160008	1	80000	100
80204	140033	70101	101	70000	100	70000	300	3569580	70134	200	80052	200	160008	1	80000	100
80204	140033	70101	101	70000	100	70000	300	3569248	70100	200	80004	200	160008	1	80000	100
80204	140033	70101	101	70000	100	70000	300	3569248	70100	200	80004	200	160008	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 14 chain cycles): 0.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	140033	70021	21	70000	20	70000	70	3569247	70020	20	80006	20	160000	11	80000	10
80025	140066	70029	21	70008	20	70034	70	3569247	70020	20	80000	20	160000	11	80000	10
80024	140033	70021	21	70000	20	70000	70	3569248	70020	20	80000	20	160000	11	80000	10
80024	140033	70021	21	70000	20	70000	70	3569248	70020	20	80000	20	160000	11	80000	10
80024	140086	70033	21	70012	20	70036	70	3569248	70020	20	80000	20	160000	11	80000	10
80024	140033	70021	21	70000	20	70000	70	3569248	70020	20	80000	20	160000	11	80000	10
80024	140033	70021	21	70000	20	70000	66	3569580	70054	20	80056	20	160000	11	80000	10
80024	140033	70021	21	70000	20	70000	70	3569248	70020	20	80000	20	160000	11	80000	10
80024	140033	70021	21	70000	20	70000	70	3569248	70020	20	80000	20	160000	11	80000	10
80024	140033	70021	21	70000	20	70000	70	3569248	70020	20	80000	20	160000	11	80000	10

Test 3: throughput

Count: 8

Code:

  mov v0.16b, v8.16b
  mov v1.16b, v8.16b
  mov v2.16b, v8.16b
  mov v3.16b, v8.16b
  mov v4.16b, v8.16b
  mov v5.16b, v8.16b
  mov v6.16b, v8.16b
  mov v7.16b, v8.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2511

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	20295	40009	101	39908	100	39912	300	159652	40012	200	80024	200	160052	1	80000	100
80204	20098	40009	101	39908	100	39912	300	159652	40012	200	80024	200	160048	1	80000	100
80204	20086	40009	101	39908	100	39912	300	159652	40012	200	80024	200	160048	1	80000	100
80204	20086	40009	101	39908	100	39912	300	159652	40012	200	80024	200	160048	1	80000	100
80204	20086	40009	101	39908	100	39912	300	159652	40012	200	80024	200	160048	1	80000	100
80204	20086	40009	101	39908	100	39912	300	159652	40012	200	80024	200	160048	1	80000	100
80204	20086	40009	101	39908	100	39912	300	159652	40012	200	80024	200	160048	1	80000	100
80204	20086	40009	101	39908	100	39912	300	159652	40012	200	80024	200	160052	1	80000	100
80204	20120	40009	101	39908	100	39912	300	159652	40012	200	80024	200	160048	1	80000	100
80204	20097	40009	101	39908	100	39912	300	159652	40012	200	80024	200	160048	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2508

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	22068	40021	21	40000	20	40004	70	160020	40024	20	80028	20	160000	11	80000	10
80024	20173	40011	21	39990	20	39990	70	159960	40010	20	80000	20	160000	11	80000	10
80024	20072	40011	21	39990	20	39990	70	159960	40010	20	80000	20	160000	11	80000	10
80024	20063	40011	21	39990	20	39990	70	159952	40008	20	80000	20	160000	11	80000	10
80024	20061	40011	21	39990	20	39990	70	159960	40010	20	80000	20	160000	11	80000	10
80024	20061	40011	21	39990	20	39990	70	159960	40010	20	80000	20	160204	11	80000	10
80024	20092	40011	21	39990	20	39990	70	159960	40010	20	80000	20	160000	11	80000	10
80024	20070	40011	21	39990	20	39990	70	159960	40010	20	80000	20	160000	11	80000	10
80024	20068	40011	21	39990	20	39990	70	159960	40010	20	80000	20	160000	11	80000	10
80024	20061	40011	21	39990	20	39990	70	159960	40010	20	80000	20	160000	11	80000	10

MOV (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations