Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ORR (vector, immediate, 4H)

Test 1: uops

Code:

  orr v0.4h, #1
  movi v0.16b, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000

Test 2: Latency 1->1

Code:

  orr v0.4h, #1
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100481010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092481002020100042010004111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010

Test 3: throughput

Count: 8

Code:

  movi v0.16b, 0
  orr v0.4h, #1
  movi v1.16b, 0
  orr v1.4h, #1
  movi v2.16b, 0
  orr v2.4h, #1
  movi v3.16b, 0
  orr v3.4h, #1
  movi v4.16b, 0
  orr v4.4h, #1
  movi v5.16b, 0
  orr v5.4h, #1
  movi v6.16b, 0
  orr v6.4h, #1
  movi v7.16b, 0
  orr v7.4h, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204405208010910180008100800123003200568011320080013200800131160000100
160204401108011010180009100800133003200528011220080012200800121160000100
160204400868010910180008100800123003200528011220080012200800121160000100
160204400868010910180008100800123003200568011320080013200800121160000100
160204400868010910180008100800123003200528011220080012200800121160000100
160204400868010910180008100800123003200528011220080012200800121160000100
160204400868010910180008100800123003200528011220080012200800121160000100
160204400868010910180008100800123003200528011220080012200800121160000100
160204400868010910180008100800123003200528011220080012200800121160000100
160204400868010910180008100800123003200528011220080012200800121160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024438478001911800081080012303200008001020800002080000116000010
160024411948001111800001080000303200008001020800002080000116000010
160024404018001111800001080000303200008001020800002080000116000010
160024404168001111800001080000303200008001020800002080048116000010
160024404928001111800001080000303200008001020800002080035116000010
160024405108001111800001080000303202008005920800492080000116000010
160024404768001111800001080000303200008001020800002080000116000010
160024404218001111800001080000303200008001020800002080000116000010
160024404578001111800001080000303200008001020800002080000116000010
160024403888001111800001080000303200008001020800002080000116000010

Test 4: throughput

Count: 16

Code:

  orr v0.4h, #1
  orr v1.4h, #1
  orr v2.4h, #1
  orr v3.4h, #1
  orr v4.4h, #1
  orr v5.4h, #1
  orr v6.4h, #1
  orr v7.4h, #1
  orr v8.4h, #1
  orr v9.4h, #1
  orr v10.4h, #1
  orr v11.4h, #1
  orr v12.4h, #1
  orr v13.4h, #1
  orr v14.4h, #1
  orr v15.4h, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800911601051011600041001600083006402081601542001600642001600151160000100
160204800351601091011600081001600123006400361601082001600122001600121160000100
160204800441601071011600061001600103006400361601082001600122001600121160000100
160204800341601051011600041001600083006400361601082001600122001600121160000100
160204800341601051011600041001600083006400361601082001600122001600121160000100
160205800681601391011600381001600503006400361601082001600122001600121160000100
160204800341601051011600041001600083006400361601082001600122001600121160000100
160204800341601051011600041001600083006402081601542001600632001600121160000100
160204800341601051011600041001600083006400441601102001600142001600141160000100
160204800441601071011600061001600103006400361601082001600122001600121160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024801121600171116000610160010306400441600202016001420160014116000010
160024800351600181116000710160011306400521600222016001520160015116000010
160024800351600191116000810160012306400521600222016001520160015116000010
160024800351600191116000810160012306400521600222016001520160061116000010
160024800461600171116000610160010306400521600222016001520160015116000010
160025800691600531116004210160054306400441600202016001420160000116000010
160024800341600111116000010160000306400001600102016000020160000116000010
160024800341600111116000010160000306400001600102016000020160000116000010
160025800681600511116004010160052306400001600102016000020160000116000010
160024800341600111116000010160000306400001600102016000020160000116000010