Icestorm: PMULL2 (1Q) measurements

Code:

  pmull2 v0.1q, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  pmull2 v0.1q, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10025	30066	10017	11	10006	10	10031	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10025	30066	10017	11	10006	10	10031	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10

Test 3: Latency 1->3

Code:

  pmull2 v0.1q, v1.2d, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	769247	10131	200	10043	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10011	11	10000	0	10	10000	30	768905	10010	20	10003	20	20000	1	10000	10
10024	30033	10011	11	10000	0	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	0	10	10000	30	769247	10041	20	10043	20	20000	1	10000	10
10024	30033	10011	11	10000	0	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	0	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	0	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	0	10	10000	30	768769	10010	20	10003	20	20000	1	10000	10
10024	30033	10011	11	10000	0	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	0	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	0	10	10000	30	768905	10010	20	10000	20	20320	1	10000	10

Test 4: throughput

Count: 8

Code:

  pmull2 v0.1q, v8.2d, v9.2d
  pmull2 v1.1q, v8.2d, v9.2d
  pmull2 v2.1q, v8.2d, v9.2d
  pmull2 v3.1q, v8.2d, v9.2d
  pmull2 v4.1q, v8.2d, v9.2d
  pmull2 v5.1q, v8.2d, v9.2d
  pmull2 v6.1q, v8.2d, v9.2d
  pmull2 v7.1q, v8.2d, v9.2d

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40101	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40047	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40038	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40038	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160150	1	80000	100
80204	40038	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40038	80105	101	80004	100	80008	300	320044	80110	200	80014	200	160024	1	80000	100
80204	40038	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40038	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40038	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40038	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40255	80015	11	80004	10	80008	30	320036	80018	20	80012	20	160000	1	80000	10
80024	40035	80011	11	80000	10	80000	30	320288	80081	20	80075	20	160024	1	80000	10
80025	40088	80079	11	80068	10	80072	30	320036	80018	20	80012	20	160000	1	80000	10
80024	40037	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80025	40087	80077	11	80066	10	80070	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40035	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40035	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40035	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40035	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40035	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10

PMULL2 (1Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations