Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PMULL (1Q)

Test 1: uops

Code:

  pmull v0.1q, v0.1d, v1.1d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->2

Code:

  pmull v0.1q, v0.1d, v1.1d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
102043003310101101100001001000030076890510100200100032000200061010000100
102043003310101101100001001000030076890510100200100032000200061010000100
102043003310101101100001001000030076890510100200100032000200061010000100
102043003310101101100001001000030076890510100200100032000200061010000100
102043003310101101100001001000030076890510100200100032000200061010000100
102043003310101101100001001000030076890510100200100032000200061010000100
102043003310101101100001001000030076890510100200100032000200061010000100
102043003310101101100001001000030076890510100200100032000200061010000100
102043003310101101100001001000030076890510100200100032000200061010000100
102043003310101101100001001000030076890510100200100032000200061010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010003202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010

Test 3: Latency 1->3

Code:

  pmull v0.1q, v1.1d, v0.1d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000320020006110000100
1020430033101011011000010010000300768905101002001000320020006110000100
1020430033101011011000010010000300768905101002001000320020006110000100
1020430033101011011000010010000300768905101002001000320020006110000100
1020430033101011011000010010000300768905101002001000320020006110000100
1020430033101011011000010010000300768905101002001000320020006110000100
1020430033101011011000010010000300768905101002001000320020006110000100
1020530066101091031000610210031300769247101312001004320220082210000100
1020430033101011011000010010000300768905101002001000320020006110000100
1020430033101011011000010010000300768905101002001000320020006110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010
1002430033100111110000101000030768905100102010000202000011000010

Test 4: throughput

Count: 8

Code:

  pmull v0.1q, v8.1d, v9.1d
  pmull v1.1q, v8.1d, v9.1d
  pmull v2.1q, v8.1d, v9.1d
  pmull v3.1q, v8.1d, v9.1d
  pmull v4.1q, v8.1d, v9.1d
  pmull v5.1q, v8.1d, v9.1d
  pmull v6.1q, v8.1d, v9.1d
  pmull v7.1q, v8.1d, v9.1d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80204400998010510180004100800083003200368010820080012200160024180000100
80204400388010510180004100800083003200368010820080012200160024180000100
80204400388010510180004100800083003200368010820080012200160024180000100
80204400388010510180004100800083003200368010820080012200160024180000100
80204400388010510180004100800083003200368010820080012200160024180000100
80204400388010510180004100800083003200368010820080012200160024180000100
80204400388010510180004100800083003200368010820080012200160390180000100
80204400388010510180004100800083003200368010820080012200160024180000100
80204400388010510180004100800083003200368010820080012200160024180000100
80204400388010510180004100800083003202928017220080075200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80024401958001511800041080008303200368001820800122016000018000010
80024400368001111800001080000303200008001020800002016000018000010
80024400358001111800001080000303200008001020800002016000018000010
80024400358001111800001080000303200008001020800002016000018000010
80024400358001111800001080000303200008001020800002016000018000010
80024400358001111800001080000303200008001020800002016000018000010
80024400358001111800001080000303200008001020800002016000018000010
80024400358001111800001080000303200008001020800002016014618000010
80024400358001111800001080000303200008001020800002016000018000010
80024400368001111800001080000303200008001020800002016000018000010