Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
pmull v0.1q, v1.1d, v2.1d eor v0.16b, v0.16b, v3.16b
movi v0.16b, 1 movi v1.16b, 2 movi v2.16b, 3
(no loop instructions)
Retires: 2.000
Issues: 1.000
Integer unit issues: 0.001
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) |
| 2004 | 1029 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 2000 | 4000 | 1 | 2000 |
| 2004 | 553 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 2000 | 4000 | 1 | 2000 |
| 2004 | 535 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 2000 | 4000 | 1 | 2000 |
| 2004 | 535 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 2000 | 4000 | 1 | 2000 |
| 2004 | 535 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 2000 | 4000 | 1 | 2000 |
| 2004 | 535 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 2000 | 4000 | 1 | 2000 |
| 2004 | 535 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 2000 | 4000 | 1 | 2000 |
| 2004 | 535 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 2000 | 4000 | 1 | 2000 |
| 2004 | 535 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 2000 | 4000 | 1 | 2000 |
| 2004 | 535 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 2000 | 4000 | 1 | 2000 |
Chain cycles: 2
Code:
pmull v0.1q, v1.1d, v2.1d eor v0.16b, v0.16b, v3.16b eor v1.16b, v1.16b, v0.16b nop
movi v0.16b, 1 movi v1.16b, 2 movi v2.16b, 3
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 2 chain cycles): 3.0033
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 0 | 60012 | 1 | 0 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 0 | 60012 | 1 | 0 | 30000 | 100 |
| 40205 | 50066 | 20110 | 103 | 20007 | 102 | 20032 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 0 | 60012 | 1 | 0 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 0 | 60012 | 1 | 0 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 0 | 60012 | 1 | 0 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 0 | 60012 | 1 | 0 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 0 | 60012 | 1 | 0 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 0 | 60012 | 1 | 0 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279424 | 20132 | 200 | 30048 | 200 | 0 | 60012 | 1 | 0 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 0 | 60012 | 1 | 0 | 30000 | 100 |
Result (median cycles for code, minus 2 chain cycles): 3.0033
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 1279085 | 20010 | 20 | 30006 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 1279085 | 20010 | 20 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 1279085 | 20010 | 20 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 1279085 | 20010 | 20 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 1279085 | 20010 | 20 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 1279085 | 20010 | 20 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 1279085 | 20010 | 20 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 1279085 | 20010 | 20 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 1279085 | 20010 | 20 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 30 | 1279085 | 20010 | 20 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
Chain cycles: 2
Code:
pmull v0.1q, v1.1d, v2.1d eor v0.16b, v0.16b, v3.16b eor v2.16b, v2.16b, v0.16b nop
movi v0.16b, 1 movi v1.16b, 2 movi v2.16b, 3
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 2 chain cycles): 3.0033
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279424 | 20132 | 200 | 30048 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
Result (median cycles for code, minus 2 chain cycles): 3.0033
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40025 | 50066 | 20018 | 11 | 20007 | 10 | 20032 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
Chain cycles: 2
Code:
pmull v0.1q, v1.1d, v2.1d eor v0.16b, v0.16b, v3.16b eor v3.16b, v3.16b, v0.16b nop
movi v0.16b, 1 movi v1.16b, 2 movi v2.16b, 3
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 2 chain cycles): 3.0033
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
| 40204 | 50033 | 20101 | 101 | 20000 | 100 | 20000 | 300 | 1279085 | 20100 | 200 | 30006 | 200 | 60012 | 1 | 30000 | 100 |
Result (median cycles for code, minus 2 chain cycles): 3.0033
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30006 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60108 | 1 | 30000 | 10 |
| 40024 | 50033 | 20011 | 11 | 20000 | 10 | 20000 | 0 | 30 | 0 | 1279085 | 20010 | 20 | 0 | 30000 | 20 | 60000 | 1 | 30000 | 10 |
Count: 8
Code:
pmull v0.1q, v8.1d, v9.1d eor v0.16b, v0.16b, v10.16b pmull v1.1q, v8.1d, v9.1d eor v1.16b, v1.16b, v10.16b pmull v2.1q, v8.1d, v9.1d eor v2.16b, v2.16b, v10.16b pmull v3.1q, v8.1d, v9.1d eor v3.16b, v3.16b, v10.16b pmull v4.1q, v8.1d, v9.1d eor v4.16b, v4.16b, v10.16b pmull v5.1q, v8.1d, v9.1d eor v5.16b, v5.16b, v10.16b pmull v6.1q, v8.1d, v9.1d eor v6.16b, v6.16b, v10.16b pmull v7.1q, v8.1d, v9.1d eor v7.16b, v7.16b, v10.16b
movi v8.16b, 9 movi v9.16b, 10 movi v10.16b, 11
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5011
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
| 160204 | 40492 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 160024 | 200 | 320048 | 1 | 160000 | 100 |
| 160204 | 40113 | 80110 | 101 | 80009 | 100 | 80013 | 300 | 320052 | 80112 | 200 | 160024 | 200 | 320048 | 1 | 160000 | 100 |
| 160204 | 40089 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 160024 | 200 | 320048 | 1 | 160000 | 100 |
| 160204 | 40089 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 160024 | 200 | 320048 | 1 | 160000 | 100 |
| 160204 | 40089 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 160024 | 200 | 320048 | 1 | 160000 | 100 |
| 160204 | 40089 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 160024 | 200 | 320048 | 1 | 160000 | 100 |
| 160204 | 40089 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 160024 | 200 | 320048 | 1 | 160000 | 100 |
| 160204 | 40089 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 160024 | 200 | 320048 | 1 | 160000 | 100 |
| 160204 | 40089 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 160024 | 200 | 320048 | 1 | 160000 | 100 |
| 160204 | 40089 | 80109 | 101 | 80008 | 100 | 80012 | 300 | 320052 | 80112 | 200 | 160024 | 200 | 320048 | 1 | 160000 | 100 |
Result (median cycles for code divided by count): 0.5052
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) |
| 160024 | 43778 | 80019 | 11 | 80008 | 10 | 80012 | 30 | 320000 | 80010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 41150 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 40436 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 40423 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 40435 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 40408 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 40411 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 40408 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 40426 | 80011 | 11 | 80000 | 10 | 80000 | 30 | 320000 | 80010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160025 | 40505 | 80073 | 11 | 80062 | 10 | 80073 | 30 | 320000 | 80010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |